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Elan Microelectronics Crop.
EM65568
130COM/ 128SEG 4096 Color STN LCD Driver
October 12, 2004 Version 1.2
Version 0.1 0.2 0.3
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
EM65568 Specification Revision History Content Initial version 1. Add Pad configuration 2. Add the shape of alignment mark 1. Rectify 256 color mode Palette5 on Page 44 Initial value 10001 10101 2. Modify DC characteristics current consumption IDD1 & IDD2, and add IDD3, IDD4, IDD5 3. Remove EXCS Modify Bias initial value 1/9 1/5 at page 57 Modify CK pin description Modify initial duty ratio at page 58 Modify display off current IDD5 1. Modify RF ratio register 2. Remove application circuit of 3 wires type and 4 wires serial interface with one chip enable signals 1. Modify VDD range: 2.2~3.3 V 2. Modify oscillation frequency of monochrome mode and variable mode on DC characteristics table Add tray information Add COF information Modify AC characteristics 1.Modify ITO value 2.Modify using external power supply at page52
Date February 11, 2003 April 10,2003 June 3, 2003
June 24, 2003 August 4, 2003 September 16, 2003 March 22,2004 March 29,2004 April 1,2004 May 20,2004 June 2,2004 October 12,2004
Caution: The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Contents
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. GENERAL DESCRIPTION ................................................................................................................................................... 4 FEATURE ................................................................................................................................................................................. 4 APPLICATIONS...................................................................................................................................................................... 4 PIN CONFIGURATIONS....................................................................................................................................................... 5 FUNCTIONAL BLOCK DIAGRAM ..................................................................................................................................15 PIN DESCRIPTION..............................................................................................................................................................17 FUNCTIONAL DESCRIPTION..........................................................................................................................................21 CONTROL REGISTER........................................................................................................................................................61 RELATIONSHIP BETWEEN SETTING AND COMMON/DISPLAY RAM ...............................................................92 ABSOLUTE MAXIMUM RATINGS..............................................................................................................................93 DC CHARACTERISTICS................................................................................................................................................94 AC CHARACTERISTIC..................................................................................................................................................98 APPLICATION CIRCUIT .............................................................................................................................................106
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
1.
General description
EM65568 is one of the industry's most advanced wide-screen STN-LCD drivers for 4096-color display. The industry's first sub-screen display function makes it possible to display different images and data in a sub-screen inside the main LCD screen. It also has a built-in display RAM, a power supply circuit for LCD drive, and an LCD controller circuit, therefore contributing to compact system design. Its partial display function realizes low power consumption. *Partial display function: A function that utilizes only part of the screen, thus reducing power consumption.
2.
Feature
4096-color display LCD outputs: Segment 128RGB(384 outputs); Common 130 outputs Display RAM capacity: 128x130x12=199680 bits Built-in display RAM and power supply circuit Partial display functions Switchable display in black and white mode Bus connection with 80-family/68-family MPU/ELAN MPU Logic power supply voltage: 2.2 to 3.3 V LCD driving voltage: 5.0 to 18 V Booster: 2 to 6 times Write system cycle: 200 ns Package: Part Number EM65568AGH EM65568AF EM65568BF Package Gold bumped chip COF COF Description NA Ver.A Ver.B Package information Page 5 Page 111 Page 112
Note: The EM65568 series has the following sub-codes depending on their shapes. H: Bare chip (Aluminum pad without bumped); GH: Gold bumped chip; F: COF package; T: TAB (TCP) package Example EM65568AGH EM65568: Elan number ; A: Package Version ; GH: Gold bumped chip
3.
Applications
Mobile phone Small PDA
* This specification is subject to be changed without notice.
4
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
4.
Pin configurations
751 752
338 337
DDRAM
EM65568
780 1
Figure 1. Pin configuration
309 308
Note: With the Elan logo in the left corner (as shown figure) and DDRAM (black color) on the left side the pin 1 is in the down left corner.
Mark U-Left D-Left
Coordinate (X,Y) -10425.0 ,375.0 -10425.0 ,-375.0
Mark U-Right D-Right
Coordinate (X,Y) 10425.0 ,375.0 10425.0 ,-375.0 U-Left and U-Right:
D-Left and D-Right: 100um
40 20 40 100um
100um
40
20 40 100um
* This specification is subject to be changed without notice.
5
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
PIN DIMENSIONS Size X 21760 36 46 63 50 (min.) 508+/-25.4 All Pad 17 +/- 3 (within die) 14 Chip center Y 1730 63 63 36 m
Item Chip size Bump Size Pad Pitch Die thickness
(excluding bumps)
Pad No. 1~26,283~308,338~751 27~282 309~337,752~780
Unit
Bump Height Minimum Bump Gap Coordinate Origin
RECOMMENDED COG ITO TRACES RESISTOR Interface V0~V4 CAP1+, CAP1-, CAP2+, CAP2-,CAP3+,CAP3CAP4+, CAP4-, CAP5+, CAP5-, Vout VDD, VEE VSSL, VSSH WRB,RDB,CSB,..., D0~D7 RESB ITO Traces resistances Max=50 Max=3K Max=5~10K
* This specification is subject to be changed without notice.
6
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
PAD Coordinates Table Coordinate (X,Y) -10434.6 ,-734.5 -10384.6 ,-734.5 -10334.6 ,-734.5 -10284.6 ,-734.5 -10234.6 ,-734.5 -10184.6 ,-734.5 -10134.6 ,-734.5 -10084.6 ,-734.5 -10034.6 ,-734.5 -9984.6 ,-734.5 -9934.6 ,-734.5 -9884.6 ,-734.5 -9834.6 ,-734.5 -9784.6 ,-734.5 -9734.6 ,-734.5 -9684.6 ,-734.5 -9634.6 ,-734.5 -9584.6 ,-734.5 -9534.6 ,-734.5 -9484.6 ,-734.5 -9434.6 ,-734.5 -9384.6 ,-734.5 -9334.6 ,-734.5 -9284.6 ,-734.5 -9234.6 ,-734.5 -9184.6 ,-734.5 -9121.6 ,-734.5 -9058.6 ,-734.5 -8995.6 ,-734.5 -8932.6 ,-734.5 -8869.6 ,-734.5 -8806.6 ,-734.5 -8743.6 ,-734.5 -8680.6 ,-734.5 -8617.6 ,-734.5 -8554.6 ,-734.5 -8491.6 ,-734.5 -8428.6 ,-734.5 -8365.6 ,-734.5 -8302.6 ,-734.5 -8239.6 ,-734.5 -8176.6 ,-734.5 -8113.6 ,-734.5 -8050.6 ,-734.5 -7987.6 ,-734.5 -7702.2 ,-734.5 -7639.2 ,-734.5 -7576.2 ,-734.5 -7513.2 ,-734.5 -7450.2 ,-734.5 Coordinate (X,Y) -7387.2 ,-734.5 -7324.2 ,-734.5 -7261.2 ,-734.5 -7198.2 ,-734.5 -7135.2 ,-734.5 -7072.2 ,-734.5 -7009.2 ,-734.5 -6946.2 ,-734.5 -6883.2 ,-734.5 -6820.2 ,-734.5 -6757.2 ,-734.5 -6694.2 ,-734.5 -6631.2 ,-734.5 -6568.2 ,-734.5 -6505.2 ,-734.5 -6442.2 ,-734.5 -6330.3 ,-734.5 -6267.3 ,-734.5 -6204.3 ,-734.5 -6141.3 ,-734.5 -6078.3 ,-734.5 -6015.3 ,-734.5 -5952.3 ,-734.5 -5889.3 ,-734.5 -5826.3 ,-734.5 -5763.3 ,-734.5 -5700.3 ,-734.5 -5637.3 ,-734.5 -5574.3 ,-734.5 -5511.3 ,-734.5 -5448.3 ,-734.5 -5385.3 ,-734.5 -5322.3 ,-734.5 -5259.3 ,-734.5 -5196.3 ,-734.5 -5133.3 ,-734.5 -4847.9 ,-734.5 -4784.9 ,-734.5 -4721.9 ,-734.5 -4658.9 ,-734.5 -4595.9 ,-734.5 -4532.9 ,-734.5 -4469.9 ,-734.5 -4406.9 ,-734.5 -4343.9 ,-734.5 -4280.9 ,-734.5 -4217.9 ,-734.5 -4154.9 ,-734.5 -4091.9 ,-734.5 -4028.9 ,-734.5
Pin NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Pad Name NC1 COM81 COM83 COM85 COM87 COM89 COM91 COM93 COM95 COM97 COM99 COM101 COM103 COM105 COM107 COM109 COM111 COM113 COM115 COM117 COM119 COM121 COM123 COM125 COM127 COMB NC2 V0 V0 V0 V0 V0 V0 V1 V1 V1 V1 V1 V1 V2 V2 V2 V2 V2 V2 V3 V3 V3 V3 V3
Pin NO 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pad Name V3 V4 V4 V4 V4 V4 V4 VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH NC3 VSSL VSSL VSSL VSSL VSSL VSSL VSSL VSSL TEST TEST TEST RESB RESB RESB CSB CSB CSB RS RS RS VSSL VSSL MS MS MS VDD VDD PS PS PS M86 M86 M86 VSSL
* This specification is subject to be changed without notice.
7
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Pin NO 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Pad Name VSSL WRB WRB WRB RDB RDB RDB VDD VDD D0 D0 D0 D1 D1 D1 D2 D2 D2 D3 D3 D3 D4 D4 D4 D5 D5 D5 D6 D6 D6 D7 D7 D7 D8 D8 D8 D9 D9 D9 D10 D10 D10 D11 D11 D11 D12 D12 D12 D13 D13
Coordinate (X,Y) -3965.9 ,-734.5 -3902.9 ,-734.5 -3839.9 ,-734.5 -3776.9 ,-734.5 -3713.9 ,-734.5 -3650.9 ,-734.5 -3587.9 ,-734.5 -3524.9 ,-734.5 -3461.9 ,-734.5 -3137.1 ,-734.5 -3074.1 ,-734.5 -3011.1 ,-734.5 -2948.1 ,-734.5 -2885.1 ,-734.5 -2822.1 ,-734.5 -2759.1 ,-734.5 -2696.1 ,-734.5 -2633.1 ,-734.5 -2570.1 ,-734.5 -2507.1 ,-734.5 -2444.1 ,-734.5 -2158.7 ,-734.5 -2095.7 ,-734.5 -2032.7 ,-734.5 -1969.7 ,-734.5 -1906.7 ,-734.5 -1843.7 ,-734.5 -1780.7 ,-734.5 -1717.7 ,-734.5 -1654.7 ,-734.5 -1591.7 ,-734.5 -1528.7 ,-734.5 -1465.7 ,-734.5 -1402.7 ,-734.5 -1339.7 ,-734.5 -1276.7 ,-734.5 -1213.7 ,-734.5 -1150.7 ,-734.5 -1087.7 ,-734.5 -1024.7 ,-734.5 -961.7 ,-734.5 -898.7 ,-734.5 -835.7 ,-734.5 -772.7 ,-734.5 -709.7 ,-734.5 -646.7 ,-734.5 -583.7 ,-734.5 -520.7 ,-734.5 -457.7 ,-734.5 -394.7 ,-734.5
Pin NO 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name D13 D14 D14 D14 D15 D15 D15 LP LP LP FLM FLM FLM M M M CLK CLK CLK VSSL VSSL CK CK CK CKS CKS CKS VDD VDD VDD VDD VDD VDD VDD VDD VBA VBA VBA VBA VBA VBA VREF VREF VREF VREF VREF VREF VEE VEE VEE
Coordinate (X,Y) -331.7 ,-734.5 -268.7 ,-734.5 -205.7 ,-734.5 -142.7 ,-734.5 -79.7 ,-734.5 -16.7 ,-734.5 46.3 ,-734.5 331.7 ,-734.5 394.7 ,-734.5 457.7 ,-734.5 520.7 ,-734.5 583.7 ,-734.5 646.7 ,-734.5 709.7 ,-734.5 772.7 ,-734.5 835.7 ,-734.5 898.7 ,-734.5 961.7 ,-734.5 1024.7 ,-734.5 1087.7 ,-734.5 1150.7 ,-734.5 1213.7 ,-734.5 1276.7 ,-734.5 1339.7 ,-734.5 1402.7 ,-734.5 1465.7 ,-734.5 1528.7 ,-734.5 1853.5 ,-734.5 1916.5 ,-734.5 1979.5 ,-734.5 2042.5 ,-734.5 2105.5 ,-734.5 2168.5 ,-734.5 2231.5 ,-734.5 2294.5 ,-734.5 2579.9 ,-734.5 2642.9 ,-734.5 2705.9 ,-734.5 2768.9 ,-734.5 2831.9 ,-734.5 2894.9 ,-734.5 2957.9 ,-734.5 3020.9 ,-734.5 3083.9 ,-734.5 3146.9 ,-734.5 3209.9 ,-734.5 3272.9 ,-734.5 3335.9 ,-734.5 3398.9 ,-734.5 3461.9 ,-734.5
* This specification is subject to be changed without notice.
8
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Pin NO 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Pad Name VEE VEE VEE VREG VREG VREG VREG VREG VREG VSSH VSSH VSSH VSSH VSSH VSSH VOUT VOUT VOUT VOUT VOUT VOUT CAP1CAP1CAP1CAP1CAP1CAP1CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP2CAP2CAP2CAP2CAP2CAP2CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP3CAP3CAP3CAP3CAP3-
Coordinate (X,Y) 3524.9 ,-734.5 3587.9 ,-734.5 3650.9 ,-734.5 3713.9 ,-734.5 3776.9 ,-734.5 3839.9 ,-734.5 3902.9 ,-734.5 3965.9 ,-734.5 4028.9 ,-734.5 4091.9 ,-734.5 4154.9 ,-734.5 4217.9 ,-734.5 4280.9 ,-734.5 4343.9 ,-734.5 4406.9 ,-734.5 4469.9 ,-734.5 4532.9 ,-734.5 4595.9 ,-734.5 4658.9 ,-734.5 4721.9 ,-734.5 4784.9 ,-734.5 4847.9 ,-734.5 4910.9 ,-734.5 4973.9 ,-734.5 5036.9 ,-734.5 5099.9 ,-734.5 5162.9 ,-734.5 5448.3 ,-734.5 5511.3 ,-734.5 5574.3 ,-734.5 5637.3 ,-734.5 5700.3 ,-734.5 5763.3 ,-734.5 5826.3 ,-734.5 5889.3 ,-734.5 5952.3 ,-734.5 6015.3 ,-734.5 6078.3 ,-734.5 6141.3 ,-734.5 6204.3 ,-734.5 6267.3 ,-734.5 6330.3 ,-734.5 6393.3 ,-734.5 6456.3 ,-734.5 6519.3 ,-734.5 6582.3 ,-734.5 6645.3 ,-734.5 6708.3 ,-734.5 6771.3 ,-734.5 6834.3 ,-734.5
Pin NO 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Pad Name CAP3CAP3+ CAP3+ CAP3+ CAP3+ CAP3+ CAP3+ CAP4CAP4CAP4CAP4CAP4CAP4CAP4+ CAP4+ CAP4+ CAP4+ CAP4+ CAP4+ CAP5CAP5CAP5CAP5CAP5CAP5CAP5+ CAP5+ CAP5+ CAP5+ CAP5+ CAP5+ NC4 COM126 COM124 COM122 COM120 COM118 COM116 COM114 COM112 COM110 COM108 COM106 COM104 COM102 COM100 COM98 COM96 COM94 COM92
Coordinate (X,Y) 6897.3 ,-734.5 6960.3 ,-734.5 7023.3 ,-734.5 7086.3 ,-734.5 7149.3 ,-734.5 7212.3 ,-734.5 7275.3 ,-734.5 7338.3 ,-734.5 7401.3 ,-734.5 7464.3 ,-734.5 7527.3 ,-734.5 7590.3 ,-734.5 7653.3 ,-734.5 7716.3 ,-734.5 7779.3 ,-734.5 7842.3 ,-734.5 7905.3 ,-734.5 7968.3 ,-734.5 8031.3 ,-734.5 8316.7 ,-734.5 8379.7 ,-734.5 8442.7 ,-734.5 8505.7 ,-734.5 8568.7 ,-734.5 8631.7 ,-734.5 8694.7 ,-734.5 8757.7 ,-734.5 8820.7 ,-734.5 8883.7 ,-734.5 8946.7 ,-734.5 9009.7 ,-734.5 9121.6 ,-734.5 9184.6 ,-734.5 9234.6 ,-734.5 9284.6 ,-734.5 9334.6 ,-734.5 9384.6 ,-734.5 9434.6 ,-734.5 9484.6 ,-734.5 9534.6 ,-734.5 9584.6 ,-734.5 9634.6 ,-734.5 9684.6 ,-734.5 9734.6 ,-734.5 9784.6 ,-734.5 9834.6 ,-734.5 9884.6 ,-734.5 9934.6 ,-734.5 9984.6 ,-734.5 10034.6 ,-734.5
* This specification is subject to be changed without notice.
9
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Pin NO 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350
Pad Name COM90 COM88 COM86 COM84 COM82 COM80 COM78 NC5 NC6 COM76 COM74 COM72 COM70 COM68 COM66 COM64 COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 NC7 NC8 COM22 COM20 COM18 COM16 COM14 COM12 COM10 COM8 COM6 COM4 COM2 COM0
Coordinate (X,Y) 10084.6 ,-734.5 10134.6 ,-734.5 10184.6 ,-734.5 10234.6 ,-734.5 10284.6 ,-734.5 10334.6 ,-734.5 10384.6 ,-734.5 10434.6 ,-734.5 10749.5 ,-700.0 10749.5 ,-650.0 10749.5 ,-600.0 10749.5 ,-550.0 10749.5 ,-500.0 10749.5 ,-450.0 10749.5 ,-400.0 10749.5 ,-350.0 10749.5 ,-300.0 10749.5 ,-250.0 10749.5 ,-200.0 10749.5 ,-150.0 10749.5 ,-100.0 10749.5 ,-50.0 10749.5 ,-0.0 10749.5 ,50.0 10749.5 ,100.0 10749.5 ,150.0 10749.5 ,200.0 10749.5 ,250.0 10749.5 ,300.0 10749.5 ,350.0 10749.5 ,400.0 10749.5 ,450.0 10749.5 ,500.0 10749.5 ,550.0 10749.5 ,600.0 10749.5 ,650.0 10749.5 ,700.0 10434.6 ,734.5 10384.6 ,734.5 10334.6 ,734.5 10284.6 ,734.5 10234.6 ,734.5 10184.6 ,734.5 10134.6 ,734.5 10084.6 ,734.5 10034.6 ,734.5 9984.6 ,734.5 9934.6 ,734.5 9884.6 ,734.5 9834.6 ,734.5
Pin NO 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
Pad Name COMA NC9 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA3 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14 SEGC14 SEGA15 SEGB15 SEGC15
Coordinate (X,Y) 9784.6 ,734.5 9734.6 ,734.5 9684.6 ,734.5 9634.6 ,734.5 9584.6 ,734.5 9534.6 ,734.5 9484.6 ,734.5 9434.6 ,734.5 9384.6 ,734.5 9334.6 ,734.5 9284.6 ,734.5 9234.6 ,734.5 9184.6 ,734.5 9134.6 ,734.5 9084.6 ,734.5 9034.6 ,734.5 8984.6 ,734.5 8934.6 ,734.5 8884.6 ,734.5 8834.6 ,734.5 8784.6 ,734.5 8734.6 ,734.5 8684.6 ,734.5 8634.6 ,734.5 8584.6 ,734.5 8534.6 ,734.5 8484.6 ,734.5 8434.6 ,734.5 8384.6 ,734.5 8334.6 ,734.5 8284.6 ,734.5 8234.6 ,734.5 8184.6 ,734.5 8134.6 ,734.5 8084.6 ,734.5 8034.6 ,734.5 7984.6 ,734.5 7934.6 ,734.5 7884.6 ,734.5 7834.6 ,734.5 7784.6 ,734.5 7734.6 ,734.5 7684.6 ,734.5 7634.6 ,734.5 7584.6 ,734.5 7534.6 ,734.5 7484.6 ,734.5 7434.6 ,734.5 7384.6 ,734.5 7334.6 ,734.5
* This specification is subject to be changed without notice.
10
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Pin NO 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450
Pad Name SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 SEGA26 SEGB26 SEGC26 SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30 SEGA31 SEGB31 SEGC31 SEGA32 SEGB32
Coordinate (X,Y) 7284.6 ,734.5 7234.6 ,734.5 7184.6 ,734.5 7134.6 ,734.5 7084.6 ,734.5 7034.6 ,734.5 6984.6 ,734.5 6934.6 ,734.5 6884.6 ,734.5 6834.6 ,734.5 6784.6 ,734.5 6734.6 ,734.5 6684.6 ,734.5 6634.6 ,734.5 6584.6 ,734.5 6534.6 ,734.5 6484.6 ,734.5 6434.6 ,734.5 6384.6 ,734.5 6334.6 ,734.5 6284.6 ,734.5 6234.6 ,734.5 6184.6 ,734.5 6134.6 ,734.5 6084.6 ,734.5 6034.6 ,734.5 5984.6 ,734.5 5934.6 ,734.5 5884.6 ,734.5 5834.6 ,734.5 5784.6 ,734.5 5734.6 ,734.5 5684.6 ,734.5 5634.6 ,734.5 5584.6 ,734.5 5534.6 ,734.5 5484.6 ,734.5 5434.6 ,734.5 5384.6 ,734.5 5334.6 ,734.5 5284.6 ,734.5 5234.6 ,734.5 5184.6 ,734.5 5134.6 ,734.5 5084.6 ,734.5 5034.6 ,734.5 4984.6 ,734.5 4934.6 ,734.5 4884.6 ,734.5 4834.6 ,734.5
Pin NO 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
Pad Name SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39 SEGA40 SEGB40 SEGC40 SEGA41 SEGB41 SEGC41 SEGA42 SEGB42 SEGC42 SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47 SEGA48 SEGB48 SEGC48 SEGA49
Coordinate (X,Y) 4784.6 ,734.5 4734.6 ,734.5 4684.6 ,734.5 4634.6 ,734.5 4584.6 ,734.5 4534.6 ,734.5 4484.6 ,734.5 4434.6 ,734.5 4384.6 ,734.5 4334.6 ,734.5 4284.6 ,734.5 4234.6 ,734.5 4184.6 ,734.5 4134.6 ,734.5 4084.6 ,734.5 4034.6 ,734.5 3984.6 ,734.5 3934.6 ,734.5 3884.6 ,734.5 3834.6 ,734.5 3784.6 ,734.5 3734.6 ,734.5 3684.6 ,734.5 3634.6 ,734.5 3584.6 ,734.5 3534.6 ,734.5 3484.6 ,734.5 3434.6 ,734.5 3384.6 ,734.5 3334.6 ,734.5 3284.6 ,734.5 3234.6 ,734.5 3184.6 ,734.5 3134.6 ,734.5 3084.6 ,734.5 3034.6 ,734.5 2984.6 ,734.5 2934.6 ,734.5 2884.6 ,734.5 2834.6 ,734.5 2784.6 ,734.5 2734.6 ,734.5 2684.6 ,734.5 2634.6 ,734.5 2584.6 ,734.5 2534.6 ,734.5 2484.6 ,734.5 2434.6 ,734.5 2384.6 ,734.5 2334.6 ,734.5
* This specification is subject to be changed without notice.
11
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Pin NO 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550
Pad Name SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 SEGC58 SEGA59 SEGB59 SEGC59 SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64 SEGB64 SEGC64 SEGA65 SEGB65 SEGC65
Coordinate (X,Y) 2284.6 ,734.5 2234.6 ,734.5 2184.6 ,734.5 2134.6 ,734.5 2084.6 ,734.5 2034.6 ,734.5 1984.6 ,734.5 1934.6 ,734.5 1884.6 ,734.5 1834.6 ,734.5 1784.6 ,734.5 1734.6 ,734.5 1684.6 ,734.5 1634.6 ,734.5 1584.6 ,734.5 1534.6 ,734.5 1484.6 ,734.5 1434.6 ,734.5 1384.6 ,734.5 1334.6 ,734.5 1284.6 ,734.5 1234.6 ,734.5 1184.6 ,734.5 1134.6 ,734.5 1084.6 ,734.5 1034.6 ,734.5 984.6 ,734.5 934.6 ,734.5 884.6 ,734.5 834.6 ,734.5 784.6 ,734.5 734.6 ,734.5 684.6 ,734.5 634.6 ,734.5 584.6 ,734.5 534.6 ,734.5 484.6 ,734.5 434.6 ,734.5 384.6 ,734.5 334.6 ,734.5 284.6 ,734.5 234.6 ,734.5 184.6 ,734.5 134.6 ,734.5 -134.6 ,734.5 -184.6 ,734.5 -234.6 ,734.5 -284.6 ,734.5 -334.6 ,734.5 -384.6 ,734.5
Pin NO 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
Pad Name SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 SEGC75 SEGA76 SEGB76 SEGC76 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80 SEGA81 SEGB81 SEGC81 SEGA82 SEGB82
Coordinate (X,Y) -434.6 ,734.5 -484.6 ,734.5 -534.6 ,734.5 -584.6 ,734.5 -634.6 ,734.5 -684.6 ,734.5 -734.6 ,734.5 -784.6 ,734.5 -834.6 ,734.5 -884.6 ,734.5 -934.6 ,734.5 -984.6 ,734.5 -1034.6 ,734.5 -1084.6 ,734.5 -1134.6 ,734.5 -1184.6 ,734.5 -1234.6 ,734.5 -1284.6 ,734.5 -1334.6 ,734.5 -1384.6 ,734.5 -1434.6 ,734.5 -1484.6 ,734.5 -1534.6 ,734.5 -1584.6 ,734.5 -1634.6 ,734.5 -1684.6 ,734.5 -1734.6 ,734.5 -1784.6 ,734.5 -1834.6 ,734.5 -1884.6 ,734.5 -1934.6 ,734.5 -1984.6 ,734.5 -2034.6 ,734.5 -2084.6 ,734.5 -2134.6 ,734.5 -2184.6 ,734.5 -2234.6 ,734.5 -2284.6 ,734.5 -2334.6 ,734.5 -2384.6 ,734.5 -2434.6 ,734.5 -2484.6 ,734.5 -2534.6 ,734.5 -2584.6 ,734.5 -2634.6 ,734.5 -2684.6 ,734.5 -2734.6 ,734.5 -2784.6 ,734.5 -2834.6 ,734.5 -2884.6 ,734.5
* This specification is subject to be changed without notice.
12
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Pin NO 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650
Pad Name SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89 SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 SEGB92 SEGC92 SEGA93 SEGB93 SEGC93 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97 SEGC97 SEGA98 SEGB98 SEGC98 SEGA99
Coordinate (X,Y) -2934.6 ,734.5 -2984.6 ,734.5 -3034.6 ,734.5 -3084.6 ,734.5 -3134.6 ,734.5 -3184.6 ,734.5 -3234.6 ,734.5 -3284.6 ,734.5 -3334.6 ,734.5 -3384.6 ,734.5 -3434.6 ,734.5 -3484.6 ,734.5 -3534.6 ,734.5 -3584.6 ,734.5 -3634.6 ,734.5 -3684.6 ,734.5 -3734.6 ,734.5 -3784.6 ,734.5 -3834.6 ,734.5 -3884.6 ,734.5 -3934.6 ,734.5 -3984.6 ,734.5 -4034.6 ,734.5 -4084.6 ,734.5 -4134.6 ,734.5 -4184.6 ,734.5 -4234.6 ,734.5 -4284.6 ,734.5 -4334.6 ,734.5 -4384.6 ,734.5 -4434.6 ,734.5 -4484.6 ,734.5 -4534.6 ,734.5 -4584.6 ,734.5 -4634.6 ,734.5 -4684.6 ,734.5 -4734.6 ,734.5 -4784.6 ,734.5 -4834.6 ,734.5 -4884.6 ,734.5 -4934.6 ,734.5 -4984.6 ,734.5 -5034.6 ,734.5 -5084.6 ,734.5 -5134.6 ,734.5 -5184.6 ,734.5 -5234.6 ,734.5 -5284.6 ,734.5 -5334.6 ,734.5 -5384.6 ,734.5
Pin NO 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
Pad Name SEGB99 SEGC99 SEGA100 SEGB100 SEGC100 SEGA101 SEGB101 SEGC101 SEGA102 SEGB102 SEGC102 SEGA103 SEGB103 SEGC103 SEGA104 SEGB104 SEGC104 SEGA105 SEGB105 SEGC105 SEGA106 SEGB106 SEGC106 SEGA107 SEGB107 SEGC107 SEGA108 SEGB108 SEGC108 SEGA109 SEGB109 SEGC109 SEGA110 SEGB110 SEGC110 SEGA111 SEGB111 SEGC111 SEGA112 SEGB112 SEGC112 SEGA113 SEGB113 SEGC113 SEGA114 SEGB114 SEGC114 SEGA115 SEGB115 SEGC115
Coordinate (X,Y) -5434.6 ,734.5 -5484.6 ,734.5 -5534.6 ,734.5 -5584.6 ,734.5 -5634.6 ,734.5 -5684.6 ,734.5 -5734.6 ,734.5 -5784.6 ,734.5 -5834.6 ,734.5 -5884.6 ,734.5 -5934.6 ,734.5 -5984.6 ,734.5 -6034.6 ,734.5 -6084.6 ,734.5 -6134.6 ,734.5 -6184.6 ,734.5 -6234.6 ,734.5 -6284.6 ,734.5 -6334.6 ,734.5 -6384.6 ,734.5 -6434.6 ,734.5 -6484.6 ,734.5 -6534.6 ,734.5 -6584.6 ,734.5 -6634.6 ,734.5 -6684.6 ,734.5 -6734.6 ,734.5 -6784.6 ,734.5 -6834.6 ,734.5 -6884.6 ,734.5 -6934.6 ,734.5 -6984.6 ,734.5 -7034.6 ,734.5 -7084.6 ,734.5 -7134.6 ,734.5 -7184.6 ,734.5 -7234.6 ,734.5 -7284.6 ,734.5 -7334.6 ,734.5 -7384.6 ,734.5 -7434.6 ,734.5 -7484.6 ,734.5 -7534.6 ,734.5 -7584.6 ,734.5 -7634.6 ,734.5 -7684.6 ,734.5 -7734.6 ,734.5 -7784.6 ,734.5 -7834.6 ,734.5 -7884.6 ,734.5
* This specification is subject to be changed without notice.
13
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Pin NO 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
Pad Name SEGA116 SEGB116 SEGC116 SEGA117 SEGB117 SEGC117 SEGA118 SEGB118 SEGC118 SEGA119 SEGB119 SEGC119 SEGA120 SEGB120 SEGC120 SEGA121 SEGB121 SEGC121 SEGA122 SEGB122 SEGC122 SEGA123 SEGB123 SEGC123 SEGA124 SEGB124 SEGC124 SEGA125 SEGB125 SEGC125 SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 NC10 COM1 COM3 COM5 COM7 COM9 COM11 COM13 COM15 COM17 COM19 COM21 COM23 COM25
Coordinate (X,Y) -7934.6 ,734.5 -7984.6 ,734.5 -8034.6 ,734.5 -8084.6 ,734.5 -8134.6 ,734.5 -8184.6 ,734.5 -8234.6 ,734.5 -8284.6 ,734.5 -8334.6 ,734.5 -8384.6 ,734.5 -8434.6 ,734.5 -8484.6 ,734.5 -8534.6 ,734.5 -8584.6 ,734.5 -8634.6 ,734.5 -8684.6 ,734.5 -8734.6 ,734.5 -8784.6 ,734.5 -8834.6 ,734.5 -8884.6 ,734.5 -8934.6 ,734.5 -8984.6 ,734.5 -9034.6 ,734.5 -9084.6 ,734.5 -9134.6 ,734.5 -9184.6 ,734.5 -9234.6 ,734.5 -9284.6 ,734.5 -9334.6 ,734.5 -9384.6 ,734.5 -9434.6 ,734.5 -9484.6 ,734.5 -9534.6 ,734.5 -9584.6 ,734.5 -9634.6 ,734.5 -9684.6 ,734.5 -9734.6 ,734.5 -9784.6 ,734.5 -9834.6 ,734.5 -9884.6 ,734.5 -9934.6 ,734.5 -9984.6 ,734.5 -10034.6 ,734.5 -10084.6 ,734.5 -10134.6 ,734.5 -10184.6 ,734.5 -10234.6 ,734.5 -10284.6 ,734.5 -10334.6 ,734.5 -10384.6 ,734.5
Pin NO 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780
Pad Name NC11 NC12 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 COM65 COM67 COM69 COM71 COM73 COM75 COM77 COM79 NC13
Coordinate (X,Y) -10434.6 ,734.5 -10749.5 ,700.0 -10749.5 ,650.0 -10749.5 ,600.0 -10749.5 ,550.0 -10749.5 ,500.0 -10749.5 ,450.0 -10749.5 ,400.0 -10749.5 ,350.0 -10749.5 ,300.0 -10749.5 ,250.0 -10749.5 ,200.0 -10749.5 ,150.0 -10749.5 ,100.0 -10749.5 ,50.0 -10749.5 ,-0.0 -10749.5 ,-50.0 -10749.5 ,-100.0 -10749.5 ,-150.0 -10749.5 ,-200.0 -10749.5 ,-250.0 -10749.5 ,-300.0 -10749.5 ,-350.0 -10749.5 ,-400.0 -10749.5 ,-450.0 -10749.5 ,-500.0 -10749.5 ,-550.0 -10749.5 ,-600.0 -10749.5 ,-650.0 -10749.5 ,-700.0
Note : For PCB layout, IC substrate must be floated or connected to VSS.
* This specification is subject to be changed without notice.
14
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
5.
Functional block diagram
5.1 System Block Diagram
SEGC127 SEGB127 SEGA127
COM127
SEGC0
SEGB0
SEGA0
COMB
COMA
COM0
VDD V0 V1 V2 V3 V4 VSS (VSSH,VSSL) CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ CAP4CAP4+ CAP5CAP5+ VOUT VEE VREF VBA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/SPOL D3/SMODE D2/EXCS D1/SDA D0/SCL
----
---------Segment Driver Gradation Selection Circuit Data Latch
Common Driver Shift Register
Line Address Decoder
Display Line Register
Display Line Counter
Voltage Converter CSB RS
Y Address Decoder
Y Address Register
Y Address Counter
Display RAM (DDRAM) 128 X 128 X (4+4+4) bits
* This specification is subject to be changed without notice.
Booster Circuit Input/Output Buffer
Pixel Display RAM (PGRAM) 128 X 2 X (4+4+4) bits X Address Decoder
RAM Interface X Address Counter
X Address Register
Alternation Circuit
Bus Holder
Instruction Decoder
Register Read
MPU Interface
OSC
Display Timing Gen.
M/S RDB WRB P/S M86 RESB TEST (E) (R/WB)
CK CKS CLK
LP FLM M
Figure 2. System Block Diagram
15
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
5.2 Power Circuit Block Diagram
Reference Voltage
+ -
VBA
+ -
V0
V1 Dividing Resistor
VREF VREG AMP
V2
VREG
+ -
+ + -
Bias Register
V3
V4
Electronic Volume Register
Booster step set Register
Impedence Converter
VEE
Booster Circuit
VOUT
CAP1+
CAP2+
CAP3+
CAP4+
CAP5-
Figure 3. Power Circuit Block Diagram
* This specification is subject to be changed without notice.
CAP5+
CAP1-
CAP2-
CAP3-
CAP4-
16
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
6.
Pin Description
Symbol VDD VSSL VSSH V0 V1 V2 V3 V4 I/O Power Supply Power Supply Power Supply Power Supply Description Power supply pin for logic circuit to +2.2 to 3.3V Ground pin for logic circuit, connect to 0V Ground pin for high voltage circuit, connected to 0V Bias power supply pin for LCD drive voltage When using an external power supply, convert impedance by using resistance-division of LCD drive power supply or operation amplifier before adding voltage to the pins. These voltages should have following relationship: VSS6.1 Power Supply Pins
6.2 LCD Power Supply Circuit Pins Symbol CAP1+ CAP1CAP2+ CAP2 CAP3+ CAP3CAP4+ CAP4CAP5+ CAP5VBA VREF VEE VOUT VREG I/O O O O O O O O O O O O I Power Supply O O Description Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP3- and CAP3+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP3- and CAP3+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP4- and CAP4+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP4- and CAP4+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP5- and CAP5+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP5- and CAP5+. 0.9 times VDD voltage output pin Voltage input pin for generating reference power source Voltage supply pin for booster circuit. Usually the same voltage level as VDD. In the case of TCP, draw it as a separate terminal. Output pin of boosted voltage in the built-in booster. The capacitor must be connected between this pin and VSS. Output pin for regulated voltage of VREG AMP. The capacitor must be connected between this pin and VSS.
* This specification is subject to be changed without notice.
17
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
6.3 System Bus Pins Symbol RESB I/O I Description Reset input pin. When RESB is "L", initialization is executed. Data bus / Signal interface related pins. When parallel interface is selected (P/S = "H"), The D7-D0 are 8-bits bi-directional data bus, connect to MPU data bus. When serial interface is selected (P/S = "L"), D0 and D1 (SCL, SDA) are used as serial interface pins. SCL: Input pin for data transfer clock SDA: Serial data input pin SMODE: Serial transfer mode select pin SPOL: RS pole select pin when 3-wires serial interface is selected. SDA data is latched at the rising edge of SCL. Internal serial/parallel conversion into 8-bit data occurs at the rising edge of 8th clock of SCL After completing data transferring, or when making no access, be sure to set SCL to "L". 8-bit bi-directional bus. Connected to MPU data bus. Used as data bus for upper 8-pins in the 16-bits access mode. Chip Select input pin. CSB = "L": accepts access from MPU CSB = "H": denies access from MPU RAM/Register select input pin. RS = "0": D7-D0 are display RAM data RS = "1": D7-D0 are control register data Read/Write control pin Select 80-family MPU type (M86 = "L") The RDB is a data read signal. When RDB is "L", D7-D0 are in an output status. Select 68-family MPU type (M86 = "H") R/WB = "H": When E is "H", D7-D0 are in an output status. R/WB = "L": The data on D7-D0 are latched at falling edge fo the E signal. Read/Write control pin Select 80-family MPU type (M86 = "L") The WRB is a data write signal. The data on D7-D0 are latched at rising edge of the WRB signal. Select 68-family MPU type (M86 = "H") Read/Write control input pin. R/W = "H": Read R/W = "L": Write MPU interface type selecting input pin. M86 = "H": 68-family interface M86 = "L": 80-family interface Fixed at either "H" or "L" Parallel/Serial interface select pin. P/S Chip select Data identification Data Read/Write Serial clock H CSB RS D0-D7 RDB, WRB L CSB RS SDA Write only SCL P/S = "H": For parallel interface. P/S = "L": For serial interface. Fix D15-D5 pins are Hi-Z, RDB and WRB pins to either "H" or "L". For testing only; usually fixed to "L".
D0/SCL D1/SDA D2 D3/SMODE D4.SPOL D5-D7
I/O
D8-D15 CSB RS
I/O I I
RDB (E)
I
WRB (R/WB)
I
M86
I
P/S
I
TEST
I
* This specification is subject to be changed without notice.
18
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
6.4 LCD Drive Circuit Signals Symbol I/O Description The LP is latch clock I/O pin. At the rising edge, count the display line counter. At the falling edge output the LCD drive signal. This pin use in master/slave multi-chip system M/S = "H": LP is output M/S = "L": LP is input I/O pin for LCD display synchronous signals (first line maker). When FLM pin is set to "H", the display start-line address is preset. This pin use in master/slave multi-chip system. In the display line counter M/S = "H": FLM is output M/S = "L": FLM is input I/O pin for alternated signals of LCD drive output. M/S = "H": M is output M/S = "L": M is input This pin use in master/slave multi-chip system. Maser/Slave mode select input pin M/S State OSC Power Supply Circuit LP FLM M CLK H Master Enable Enable Output Output Output Output L Slave Disable Disable Input Input Input Input Fix to "H" or "L" at this terminal. Segment output pins for LCD drives. According to the data of the Display RAM data, non-lighted at "0", lighted at "1" (Normal Mode). non-lighted at "1", lighted at "0" (Reverse Mode) and, by a combination of M signal and display data, one signal level among V0,V2,V3 and VSS signal levels are selected. (When Monochrome Display)
M Signal
LP
I/O
FLM
I/O
M
I/O
M/S
I
SEGA0-A127 SEGB0-B127 SEGC0-C127
O
Display RAM Data Normal Mode Reverse Mode V2 V0 V0 V2 V3 VSS VSS V3
Common output pins for LCD drivers. By a combination of the scanning data and M signal, one signal level among V0, V1, V4 and VSS signal level is selected. COM0COM127 O Data M Output level H H VSS L H V1 H L V0 L L V4 Common output pin for LCD drive exclusively for icons. Common output pin for LCD drive exclusively for icons.
COMA COMB
O O
* This specification is subject to be changed without notice.
19
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
6.5 Oscillating Circuit Pin Symbol CKS CK CLK I/O I I I/O Description Display timing clock source select input pin. CKS = "H": Use external clock from CK pin. CKS = "L": Use internal oscillated clock. In the slave mode, fix this pin at "L". In the case of TCP, draw it as a separate terminal. External clock input pin for display timing (CKS=1). When using internal oscillated clock (CKS=0), CK must be connected to VSS. I/O pin for display timing clock. To use this pin in the master/slave system. M/S = "H": Output display timing clock. M/S = "L": Input display timing clock from the master.
* This specification is subject to be changed without notice.
20
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.
Functional Description
7.1 MPU Interface 7.1.1 Selection of Interface Type The EM65568 transfers data through 8-bit parallel I/O (D7-D0), 16-bit parallel I/O (D15-D0) or serial data input (SDA, SCL). The parallel interface or serial interface can select by state of P/S pin. When select serial interface, data reading cannot be performed, only data writing can operate. P/S H L I/F Type Parallel Serial CSB CSB CSB RS RS RS RDB RDB WRB WRB M86 M86 SDA SDA SCL SCL Data D7~D0 (D15~D0) -
7.1.2 Parallel Input When parallel interface is selected with the P/S pin, the EM65568 allows data to be transferred in parallel to an 8-bit/16-bit MPU through the data bus. For the 8-bit/16-bit MPU, either the 80-family MPU interface or the 68-family MPU interface can be selected with the m86 pin. M86 H L MPU Type 68-family MPU 80-family MPU CSB CSB CSB RS RS RS RDB E RDB WRB R/WB WRB Data D7~D0 (D15~D0) D0~D7 (D15~D0)
7.1.3 Read/Write functions of Register and display RAM The EM65568 have four read/write functions at parallel interface mode. Each read/write function select by combinations of RS, RDB and WRB signals. RS 1 1 0 0 68-family R/WB 1 0 1 0 80-family RDB WRB 0 1 1 0 0 1 1 0 Function Read internal Register Write internal Register Read display data Write display data
7.1.4 Serial Interface EM65568 has two types serial interface. One is a 3-wires type serial interface; other one is a 4-wires type serial interface. The 3-wire or 4-wire is determined by SMODE pin. SMODE = "L": 4-wires serial interface SMODE = "H": 3-wires serial interface 7.1.5 4 Wires Serial Interface When chip select is active (CSB = "L"), 4-wires type serial interface can work through the SDA and SCL input pins. When chip select is inactive (CSB = "H"), the internal shift register and counter are reset in the initial condition. Serial data SDA are input sequentially in order of D7 to D0 at the rising of serial clock (SCL) and are converted into 8-bit parallel data (by serial to parallel conversion) at the rising edge of the 8th serial clock, being processed in accordance with the data. The identification whether are serial data inputs (SDA) are display data or control register data is judged by input to RS pin. * This specification is subject to be changed without notice. 21 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
RS = "L": display RAM data RS = "H": control register data After completing 8-bit data transferring, or when making no access, be sure to set serial clock input (SCL) to "L". Cares of SDA and SCL signals against external noise should be taken in board writing. To prevent transfer error due to external noise, release chip select (CSB = "H") every completion of 8-bit data transferring.
CSB RS SDA SCL
1 2 3 4 5 6 7 8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4. 4-Wires type Serial Interface
7.1.6 3 Wires Type Serial Interface When chip select is active (CSB = "L"), 3-wires type serial interface can work through the SDA and SCL input pins. When chip select is inactive (CSB = "H"), the internal shift register and counter are reset in the initial condition. Serial data SDA are input sequentially in order of RS, D7 to D0 at the rising edge of serial clock (SCL) and are converter into 9-bit parallel data (by serial to parallel conversion) at the rising edge of the 9th serial clock. The identification whether the serial data inputs (SDA) are display data or control register data is determined by first serial input data (RS) and SPOL pin as followed. RS 0 1 SPOL = "0" Display RAM/Register Display RAM Data Control Register Data RS 0 1 SPOL = "1" Display RAM/Register Control Register Data Display RAM Data
After completing 9-bits data transferring, or when making no access, be sure to set serial clock input (SCL) to "L". Cares of SDA and SCL signals against external noise should be taken in board wiring. To prevent transfer error due to external noise, release chip select (CSB = "H") every completion of 9-bit data transferring.
CSB SDA SCL
1 2 3 4 5 6 7 8 9
RS
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. 3-Wires Type Serial Interface 7.1.7 Chip Select Connection in Serial Interface Mode When serial interface use in 2 chips EM65568 system; one is a Master another is a slave, both EM65568 can control by only one chip select signal.
* This specification is subject to be changed without notice.
22
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.2 Data write to Display RAM and Control Register The data write to display RAM and Control Register use almost same procedure, only different setting of RS that select access object. RS = "L": Display RAM data RS = "H": Control register data In the case of the 80-family MPU, the data is written at the rising edge of WRB. In the case of the 68-family MPU, the data is written at the falling edge of signal E. Data write operation
D0~D7 (D0~D15) WRB RS Wrie to which Wrie to control register Wrie to display RAM
Data0 Data1 Data2 Data3 Data4
Figure 6. Data write operation 7.3 Internal Register Read In the case of display RAM read operation, need dummy read one time. The designated address data are not output to read operation immediately after the address set to AX or AY register, but are output when the second data read. Dummy read is always required one time after address set and write cycle.
* This specification is subject to be changed without notice.
23
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Read display RAM operation
W RB D0~D7 (D0~D15) RDB RS
n
Address set (AX,AY) Address = n
***
Dummy Read
n
Data Read Address=n
n+1
Data Read Address=n+1
n+2
Data Read Address=n+2
Figure 7. Read display RAM operation The EM65568 can be read the control registers, in case of control register read operation, data bus upper nibble (D7-D4) use for register address (0 to FH). In maximum, 16 registers can access directly. But number of register is more than 16 registers. Therefore, EM65568 has register bank control. The RE register is set bank number to access. And the RE address is 0FH, in any bank can access RE register. It is need 4-steps to read the specific register in maximum case. (1) Write 04H to RE register for access to RA register. (2) Writes specific register address to RA register. (3) Write specific register bank to RE register. (4) Read specific register contents. Register read operation
W RB D0~D7
04H
Bank number write to RE for RA
addr
Address write to RA
bank
Bank number write to RE
data
read specific register
RDB RS
Figure 8. Register read operation 7.4 16-bit Data Access to Display RAM The EM65568 correspond to 8-bits and 16-bits bus size access. The data bus size can select by WLS register. WLS = "0": 8-bits bus size WLS = "1": 16-bits bus size In the 16-bits access mode, access for control register use low-byte data bus (D7~D0). Then high byte data bus (D15~D8) are not used in internal circuit. When read control register using 16-bits bus. Register values output to D3-D0 and D15-D4 output "H".
* This specification is subject to be changed without notice.
24
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.5 Display Start Address Register This register determines the Y-address of the display RAM corresponding to the display start line. The display RAM data that addressed Display Start Address register output to common driver start line. The actual common start line of LCD panel depend on Display Start Common register and SHIFT bit of Display Control register. The register are preset every timing of FLM signal variation in the display line counter. The line counter counts up being synchronized with LP input and generates line addresses which read out sequentially 384 bits data from display RAM to LCD drive circuit. 7.6 Addressing of Display RAM The EM65568 has built-in bit mapped display RAM. The display RAM consists of 1536 bits (12 bits*128) in the X-direction and 130 bits in the Y-direction. In the gradation display mode, the EM65568 provides segment driver output for 16-gradation display using 4 bits. The three outputs of the segment driver can be used for one pixel of RGB. When connected to an STN color LCD panel, the EM65568 can display 128*130 pixels with 4096 colors (16 gradation * 16 gradation * 16 gradation). The address area in the X-direction depends on the access bus size. In the X-direction, X Address register use to access; and in the Y-direction, Y Address register use to access. Do not specify any address outside the effective address area in each access mode because it is not permitted. In Gradation Display Mode (MON="0" ) 8-bits bus size access ABS=0 X-address 0H 1H ----------------------------------------------------------------- FEH FFH 0H 7bit 5bit 7bit 5bit ---------------81H 7bit 5bit ABS=1 X-address 0H 1H ----------------------------------------------------------------- FEH FFH 0H 4bit 8bit 4bit 8bit ---------------81H 4bit 8bit 4bit 8bit 25 2005/3/8 (V1.2) 7bit 5bit
Y-address
Y-address
* This specification is subject to be changed without notice.
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
HSW=1 X-address 0H 1H ----------------------------------------------------------------- BEH BFH 0H 8bit 8bit 8bit 8bit ---------------81H 8bit 8bit C256=1 X-address 0H 1H ----------------------------------------------------------------- 7EH 7FH 0H 8bit 8bit 8bit 8bit ---------------81H 8bit 8bit 8bit 8bit X-address 0H --------------------------------------------------------------------- 7FH 0H 12bit 12bit ---------------81H 12bit C256=1 X-address 0H --------------------------------------------------------------------- 3FH 0H 16bit 16bit ---------------81H 16bit 16bit 26 2005/3/8 (V1.2) 12bit 8bit 8bit
Y-address
Y-address
16-bits bus size access
Y-address
Y-address
The addresses, X Address and Y Address are possible to be set up so that they can increment automatically with the address control register. The increment is made every time display RAM is read or written from MPU. In the Y-direction, 384 bits of data are read out to the display data latch circuit by internal operation when the LP rises in a one-line cycle. They are output * This specification is subject to be changed without notice.
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
from the display data latch circuit when the LP fails. When FLM signals being output in one frame cycle are at "H", the values in the display starting line register are preset in the line counter and the line counter counts up at the falling of LP signals. The display line address counter is synchronized with each timing signal of the LCD system to operate and is independent of address counters X and Y. 7.7 Display RAM access using Windows Function The EM65568 has window area setting command for specified display RAM area access. For use window function, need to set up two position's X and Y address. Also need set up auto increment mode (AXI="1", AYI="1"). Two position means window start position and window end position. The window start position's X and Y address set to normal X address(AX) and Y address(AY) registers. The window end position's X and Y address set to Window X End Address (EX) and Window Y Enc Address (EY) register. In window function access, can use modify write access with set to AIM="1". In case of using window function access, should be set following registers before access to RAM. WIN = "1", AXI="1", AYI="1" X Address, Y Address, Window X End Address, Window Y End Address Moreover, should be keep following address condition. Window end X address(EX) Window start X address (AX) Window end Y address(EY) Window start X address (AY) X direction (X,Y) Start Address Y direction Window access area All display RAM area 7.8 Display RAM Data and LCD (only monochrome mode) One bit of display RAM data corresponds to one dot of LCD. Normal display and reverse display by REV register are set up as follows. Normal display (REV=0): RAM data = "0" not lighted RAM data = "1" lighted Reverse display (REV=1): RAM data = "0" lighted RAM data = "1" not lighted (X,Y) End Address * This specification is subject to be changed without notice. 27 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.9 Segment Display Output Order/Reverse Set up The order of display output, SEGA0, SEGB0, SEGC0 to SEGA127, SEGB127, and SEGC127 can be reversed. If REF control bit set to "1", display by reversing access to display RAM from MPU by using REF register, lessen the limitation in placing IC when assembling an LCD panel module. 7.10 Relationship between Display RAM and Address The Display RAM block diagram shows in the figure below:
Bit-order reverse Write:depend on REF,SWAP Read:depend on REF
Internal Data Bus Bit order reverse
Read Data
Grayscale Conversion Data
SEGMENT Output I/F Data conversion is Conversion depend on MON, REF,SWAP,GLSB Segment data
Display start address
Write Data Effective Y address
MPU I/F
The EM65568 execute address conversion that depends on control register setting. In case of auto increment mode, usually AX register is added one. For instance when REF and AXI are both "1", AX register is added one, but effective X address seems decrement because of address conversion. The effective Y address use AY register values as it is.
* This specification is subject to be changed without notice.
AY Register
Display RAM
X-Address (00H~FFH)
Effective X address
Address conversion circuit
Address conversion is depend on MON,WLS,REF setting Valid maximum is depend on MON,WLS,WIN,HSW,C256 setting
AX Register
Figure 10. The Display RAM block diagram
LA Register
Y-Address (00H~81H)
Counter
28
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(1) Monochrome mode, 8-bits Access mode HSW ABS REF SWAP 0 0 0 0 0 0 1 1 D0 D1 X address / Data bus / Segment assign X=01H X=FEH X=FFH X=00H D6 D7 D1 D2 D3 D4 D7 D0 D1 D2 D4 D5 D6 D7 D1
X=00H X=FEH D2 D4 D5
X=FFH X=01H D2 D3 D3 D5 D5 D4 D4 D6 D6 D7 SEGA127 D7 SEGC127 D4 D7 SEGA127 D4 D7 SEGC127 X=FFH X=01H D6 D7 D2 D2 D1 SEGB127 2005/3/8 (V1.2) D3 SEGB127 X=FFH X=01H D1 D3 SEGB127 X=FFH X=01H D1 D2
SEGA127
HSW ABS REF SWAP 0 0 0 1 0 0 1 0 D0 D1
X=00H X=FEH D2 D4 D5 D6 D7
X address / Data bus / Segment assign X=01H X=FEH X=FFH X=00H D1 D2 D3 D4 D7 D0 D1 D2 D4 D5
HSW ABS REF SWAP 0 1 0 0 0 1 1 1 D0
X=00H X=FEH D1 D2 D3 D0 D1 D2
X address / Data bus / Segment assign X=01H X=FEH X=FFH X=00H D3 D4 D5 D6 D7 D0 D1 D2 D3 D0
HSW ABS REF SWAP 0 1 0 1 0 1 1 0 D0
X=00H X=FEH D1 D2 D3 D0 D1 D2
X address / Data bus / Segment assign X=01H X=FEH X=FFH X=00H D3 D4 D5 D6 D7 D0 D1 D2 D3 D0
* This specification is subject to be changed without notice.
29
SEGC127
SEGA0
SEGC0
SEGB0
SEGA127
SEGA0
SEGB0
SEGC0
SEGC127
SEGA0
SEGC0
SEGB0
SEGB127
SEGA0
SEGB0
SEGC0
HSW 1
HSW 1
X=BEH
X=BEH
SEGA0 ABS * ABS *
SEGC0
HSW ABS REF SWAP 1 * 0 1
HSW ABS REF SWAP 1 * 0 0
X=BFH
X=BFH
REF SWAP 1 1
REF SWAP 1 0
SEGB0
SEGB0
SEGC0 X=00H SEGC0
SEGA0
X=00H
SEGA0
SEGA1 SEGB0
SEGC1
* This specification is subject to be changed without notice. SEGB1 SEGB0 SEGA1 SEGA0 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 SEGC0 SEGC126 SEGC1 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SEGA1 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 X address / Data bus / Segment assign X=BDH X=BEH X=01H X=02H X address / Data bus / Segment assign X=BDH X=BEH X=01H X=02H SEGB126 X address / Data bus / Segment assign X=01H X=BEH X address / Data bus / Segment assign X=01H X=BEH SEGA126 SEGC126 SEGA126 SEGC127 X=00H SEGA127 X=00H SEGC127 X=BFH X=BFH SEGB127 X=01H SEGB127 X=01H SEGB127 SEGA127 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 SEGA127 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SEGC127 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SEGB1
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
30
SEGC1
D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3
SEGA126
SEGB126
SEGC126
SEGA127
2005/3/8 (V1.2)
SEGB127
SEGC127
D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(2) Monochrome mode, 16-bits Access mode, Display Start Address = "00H" HSW ABS REF SWAP * 0 0 0 * 0 1 1 D1 D2 D3 D4 D7 X address / Data bus / Segment assign X=00H X=7FH D10 D12 D13 D14 D15 D8 D9 D1 D2 D3 D4 D7 X=7FH X=00H D10 D12 D13 D13 D9 D9 D14 D14 D10 D10 D15 SEGA127 D11 SEGC127 D8 D11 SEGA127 D8 D15 SEGC127 D12 D8 D8 D5 D5 D9 D9 D6 D6
SEGA127
HSW ABS REF SWAP * 0 0 1 * 0 1 0 D1 D2 D3 D4 D7
X address / Data bus / Segment assign X=00H X=7FH D10 D12 D13 D14 D15 D8 D9 D1 D2 D3 D4 D7 X=7FH X=00H D10 SEGB127 2005/3/8 (V1.2) D7 SEGB127 X=7FH X=00H D10 D11 D7 D8 D9 D0 D1 D2 D3 D4 D7 SEGB127 X=7FH X=00H D10 D11 D7 D8 D9 D0 D1 D2 D3 D4
HSW ABS REF SWAP * 1 0 0 * 1 1 1 D0 D1 D2 D3 D4
X address / Data bus / Segment assign X=00H X=7FH D5 D6
HSW ABS REF SWAP * 1 0 1 * 1 1 0 D0 D1 D2 D3 D4
X address / Data bus / Segment assign X=00H X=7FH D5 D6
* This specification is subject to be changed without notice.
31
SEGC127
SEGA0
SEGC0
SEGB0
SEGA127
SEGA0
SEGB0
SEGC0
SEGC127
SEGA0
SEGC0
SEGB0
SEGB127
SEGA0
SEGB0
SEGC0
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(3) Gradation mode(4096 color), 8 bits access mode HSW ABS REF SWAP 0 0 0 0 0 0 1 1
D0 D1
X=00H X=FEH
D2 D4 D5 D6
X address / Data bus / Palette / Segment assign X=01H X=FEH X=FFH X=00H
D7 D1 D2 D3 D4 D7 D0 D1 D2 D4 D5 D6 D7 D1
X=FFH X=01H
D2 D3 D4 D4 D7
Palette A
Palette B
Palette C
Palette A
Palette B
SEG A127
SEG B127
HSW ABS REF SWAP 0 0 0 1 0 0 1 0
D0 D1
X=00H X=FEH
D2 D4 D5 D6
X address / Data bus / Palette / Segment assign X=01H X=FEH X=FFH X=00H
D7 D1 D2 D3 D4 D7 D0 D1 D2 D4 D5 D6 D7 D1
X=FFH X=01H
D2 D3 D7
Palette A
Palette B
Palette C
Palette A
Palette B
SEG C127
SEG B127
SEG C0
SEG B0
HSW ABS REF SWAP 0 1 0 0 0 1 1 1 D0
X=00H X=FEH D1 D2 D3 D0 D1
X address / Data bus / Palette / Segment assign X=01H X=FEH X=FFH X=00H D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D0 D1 D2
SEG A0
X=FFH X=01H D3 D4 D5 D5 D6 D6 D7 D7
Palette A
Palette B
Palette C
Palette A
Palette B
SEG A127
SEG B127
HSW ABS REF SWAP 0 1 0 1 0 1 1 0 D0
X=00H X=FEH D1 D2 D3 D0 D1
X address / Data bus / Palette / Segment assign X=01H X=FEH X=FFH X=00H D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D0 D1 D2
X=FFH X=01H D3 D4
Palette A
Palette B
Palette C
Palette A
Palette B
* This specification is subject to be changed without notice.
32
2005/3/8 (V1.2)
SEG A127
SEG C127
SEG B127
SEG C0
SEG B0
SEG A0
Palette C
SEG C127
SEG A0
SEG B0
SEG C0
Palette C
SEG A12 7
Palette C
SEG C127
SEG A0
SEG B0
SEG C0
Palette C
SEG A0 HSW 1 HSW 1 X=BEH
Palette A
X=BEH
Palette A
SEG C0 ABS * SEG B0
Palette B
ABS *
SEG B0 X=BFH SEG A0
Palette C
HSW ABS REF SWAP 1 * 0 1
HSW ABS REF SWAP 1 * 0 0
Palette B
X=BFH
REF SWAP 1 1
REF SWAP 1 0
SEG C0 SEG C1
Palette A
Palette C
SEG A1 X=00H SEG B0
Palette B SEG B0
Palette A
SEG C0
Palette A SEG A0
Palette A
X=00H
* This specification is subject to be changed without notice. SEG B1
Palette B Palette B
SEG B1 SEG A1
Palette C Palette C
Palette B
SEG C1
Palette C
D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 SEG A0
SEG C0 Palette C
X address / Data bus / Palette / Segment assign X=BDH X=BEH X=01H X=02H
X address / Data bus / Palette / Segment assign X=BDH X=BEH X=01H X=02H
X address / Data bus / Palette / Segment assign X=01H X=BEH
X address / Data bus / Palette / Segment assign X=01H X=BEH
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
33 SEG C126
Palette A
D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 SEG C1
Palette A
SEG A126 SEG B126
Palette B
Palette A
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SEG A1 Palette A
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SEG B126 SEG A126
Palette C
Palette B
SEG A126
Palette C
SEG C126
Palette C
SEG C126 SEG C127
Palette A
Palette C
SEG A127 SEG B127
Palette B
Palette A
SEG C127 X=00H
Palette A
SEG A127
Palette A
X=00H
2005/3/8 (V1.2) SEG A127
Palette C
SEG B127
Palette B
SEG B127
Palette B
SEG B127
Palette B
X=BFH
X=BFH
X=01H
X=01H
SEG C127
Palette C
D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 SEG A127
Palette C
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SEG C127
Palette C
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
HSW ABS REF SWAP * 0 0 0 * 0 1 1
HSW ABS REF SWAP * 1 0 1 * 1 1 0 D0 D1 SEG C0
Palette A
HSW ABS REF SWAP * 1 0 0 * 1 1 1
HSW ABS REF SWAP * 0 0 1 * 0 1 0
D0 D1 SEG A0
Palette A
SEG C0
Palette A
Palette A
D1 SEG A0 D2 D3 D4 D7 SEG B0
Palette B
D1 D2 D3 D4 D5 D8 D9 D10 D12 SEG A0
Palette C
D2 D3 D4 D7 D8
D2
D3
D4 SEG B0
Palette B
(3) Gradation mode (4096 color), 16 bits access mode
* This specification is subject to be changed without notice. D6 D7 D8 SEG C0
Palette C
SEG B0
Palette B
D5
D6
SEG B0
Palette B
D9 D10 D12 SEG C0
Palette C
D7 D9 D13 D14 D15 D15 SEG C127
Palette A
X address / Data bus / Palette / Segment assign X=00H X=7FH X=7FH X=00H
X address / Data bus / Palette / Segment assign X=00H X=7FH X=7FH X=00H
X address / Data bus / Palette / Segment assign X=00H X=7FH X=7FH X=00H
X address / Data bus / Palette / Segment assign X=00H X=7FH X=7FH X=00H
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
34 D10 D11 D0 SEG A127
Palette A
D8
SEG A0
Palette C
D9
D13 D14 D15 D1
D10
D11
D0 D1 D2 D3 D4 SEG B127
Palette B
SEG C127
Palette A
D1
D14 D13 D12 D10
Palette B
D2
SEG A127
Palette A
D2 D3 D4 D7 D9 D8
D3 D5 D6 D7 D8 SEG C127
Palette C
D4
SEG B127
Palette B
D5
D6
SEG B127
D8 D7 D4 D3
SEG B127
Palette B
D9 D10 D12 D13
D7 D9
D8
2005/3/8 (V1.2) D10 D11
SEG A127
Palette C
D9
D10
SEG A127
Palette C
D2 D1
SEG C127
Palette C
D14 D15
D11
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(5)Gradation mode(256 Color) ,(C256=1) 8-bit mode(WLS=0) HSW ABS REF SWAP * * 0 0 * * 1 1
D0 D1 D2
X address / Data bus / Palette / palette bit / Segment assign X=00H X=7FH X=7FH X=00H
D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 C2 D6 C2 Palette C B3 C1 D4 D5 D7 C3 D7 C3
Palette A
Palette B
Palette C
Palette A
A2
A3
A2
A3
B1
B2
B3
C1
C2
C3
B1
SEG A127
SEG B127
B2
Palette B
HSW ABS REF SWAP * * 0 1 * * 1 0
D0 D1 D2
X address / Data bus / Palette / palette bit / Segment assign X=00H X=7FH X=7FH X=00H
D3 D4 D5 D6 D7 D0 D1 D2 D3
Palette A
Palette B
Palette C
Palette A
Palette B
A2
A3
A2
A3
B1
B2
B3
C1
C2
C3
B1
B2
B3
C1
* This specification is subject to be changed without notice.
35
2005/3/8 (V1.2)
SEG A127
SEG C127
SEG B127
SEG C0
SEG B0
SEG A0
Palette C
SEG C127
SEG A0
SEG B0
SEG C0
16-bit mode(WLS=1)
HSW ABS REF SWAP * * 0 1 * * 1 0
HSW ABS REF SWAP * * 0 0 * * 1 1
A2 A3 B1 B2 B3 C1 C2 C3 A2 A3 B1 B2 B3 C1 C2 C3 A2 A3 B1 B2 B3 C1 C2 C3 A2 A3 B1 B2 B3 C1 C2 C3 Palette C Palette A Palette B Palette B Palette A Palette C Palette B Palette A A3 B1 B2 B3 C1 C3 A2 Palette C C2 B3 C1 Palette C Palette A Palette B Palette B B2 Palette A A3 B1 Palette B Palette A
SEG A1
A2
SEG A0 SEG B0 SEG C0 SEG A1 SEG B1 SEG C1
SEG B1 SEG C1 SEG A0 SEG B0 SEG C0
* This specification is subject to be changed without notice.
C2 C3 A2 A3 B1
X address / Data bus / Palette / palette bit / Segment assign X=00H X=3FH X=3FH X=00H
X address / Data bus / Palette / palette bit / Segment assign X=00H X=3FH X=3FH X=00H
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
36 SEG A127 SEG B127 SEG C127 SEG A126 SEG B126 SEG C126 SEG A126 SEG B126 SEG C126 SEG A127 SEG B127
Palette C
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Palette C Palette A B2 B3 C1 C2 C3 A2 A3 B1 B2 B3 C1 Palette B Palette C Palette A Palette B
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
2005/3/8 (V1.2)
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
SEG C127
C2 C3
Palette C
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(6)Data read and write bit assignment In 16-bit data bus mode ABS=0 C256=0 Write Read ABS=1 C256=0 Write Read ABS=* C256=1 Write Read D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 1 D10 D9 D15 D14 D13 D12 D11 D10 D9 1 1 1 1 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D8 D8 D8 D8 D8 D8 D7 D7 D7 D7 D7 D7 D6 1 D6 D6 D6 D6 D5 1 D5 D5 D5 D5 D4 D4 D4 D4 D4 D4 D3 D3 D3 D3 D3 D3 D2 D2 D2 D2 D2 D2 D1 D1 D1 D1 D1 D1 D0 1 D0 D0 D0 D0
In 8-bit data bus mode ABS=0 HSW=0 C256=0 Address 00,02,04.........FC,FEH 01,03,05.........FD,FFH Write D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Read D7 D6 D5 D4 1 D2 D1 D0 D7 1 1 D4 D3 D2 D1 1 ABS=1 HSW=0 C256=0 Address 00,02,04.........FC,FEH 01,03,05.........FD,FFH Write D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Read 1 1 1 1 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ABS=0 HSW=1 C256=0 Address 00,01,02......BD,BE,BFH Write D7 D6 D5 D4 D3 D2 D1 D0 Read D7 D6 D5 D4 D3 D2 D1 D0 ABS=0 HSW=0 C256=1 Address 00,01,02......7D,7E,7FH Write D7 D6 D5 D4 D3 D2 D1 D0 Read D7 D6 D5 D4 D3 D2 D1 D0
7.11 Display Data Structure and Gradation Control For the purpose of gradation control, one pixel requires multiple bits of display RAM. The EM65568 has 4-bit data per output to achieve the gradation display. The three outputs of the segment driver are used for one pixel of RGB, and the EM65568 is connected to an STN color LCD panel. It can display 128*130 pixels with 4096 colors (4 bits * 4 bits * 4 bits). In this case, since the gradation display data is processed by a single access to the memory, the data can be rewritten fast and naturally. The weighting for each data bit is dependent on the status of the SWAP bit and the REF bit that is selected when data is written to the display RAM.
* This specification is subject to be changed without notice.
37
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(1) Gradation mode (4096 color) 8-bit mode (REF, SWAP)=(0,0) or (1,1)
SEGAi SEGBi SEGCi
i=0 to 127
palette Aj
palette Bj
palette Cj
Gradation palette j=0 to 15
Gradation control
0
LSB
0
0
0
M SB
1
LSB
0
0
0
M SB
1
LSB
1
1
1
M SB
display RAM data
0 D0
0 D1 D1 D1
0 D2 D2 D2
0 D4 D3
1
0
0
0
1 D2 D4
1 D3 D5
1 D4 D6
1 D7 D7
D5 D6 D0 D1
D7 D1 D2 D3
MPU write data X address: 2nH,2n+1H
ABS=1 HSW=1
D0 D0
D3 D4 D5 D6 D7 D0 D1 D2 D3 Note : Internal X address : 2nH ,2n+1H (REF="0") : (FE-2n)H , [FF-(2n+1)]H (REF="1") In HSW =1, Address=00H~BFH
(REF, SWAP)=(0,1) or (1,0)
SEGAi
SEGBi
SEGCi
i=0 to 127
palette Cj
palette Bj
palette Aj
Gradation palette j=0 to 15
Gradation control
1
M SB
1
1
1
LSB
0
M SB
0
0
1
LSB
0
M SB
0
0
0
LSB
display RAM data
0 D0
0 D1 D1 D1
0 D2 D2 D2
0 D4 D3
1
0
0
0
1 D2 D4
1 D3 D5
1 D4 D6
1 D7 D7
MPU write data X address: 2nH,2n+1H
D5 D6 D0 D1
D7 D1 D2 D3
ABS=1 HSW=1
D0 D0
D3 D4 D5 D6 D7 D0 D1 D2 D3 Note : Internal X address : 2nH ,2n+1H (REF="0") : (FE-2n)H , [FF-(2n+1)]H (REF="1") In HSW =1, Address=00H~BFH
* This specification is subject to be changed without notice.
38
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
16-bit mode In 16-bits access, the weighting for each data bit is dependent on the status of the SWAP bit and the REF bit that is selected when data is written to the display RAM, as in the case with 8-bits access. (REF, SWAP)=(0,0) or (1,1)
SEGAi SEGBi SEGCi
i=0 to 127
palette Aj
palette Bj
palette Cj
Gradation palette j=0 to 15
Gradation control
0
LSB
0
0
0
M SB
1
LSB
0
0
0
M SB
1
LSB
1
1
1
M SB
display RAM data
0 D1
0 D2 D1
0 D3 D2
0 D4 D3
1
0
0
0
1 D8
1
1
1
MPU write data X address: nH
D7 D8 D4 D5
D9 D10 D12 D13 D14 D15 D6 D7 D9 D10 D11
ABS=1
D0
Note : Internal X address : nH (REF="0") : 7FH-nH (REF="1")
(REF, SWAP)=(0,1) or (1,0)
SEGAi SEGBi SEGCi
i=0 to 127
palette Cj
palette Bj
palette Aj
Gradation palette j=0 to 15
Gradation control
1
M SB
1
1
1
LSB
0
M SB
0
0
1
LSB
0
M SB
0
0
0
LSB
display RAM data
0 D1
0 D2 D1
0 D3 D2
0 D4
1
0
0
0
1
1
1
1
MPU write data X address: nH
D7 D8
D9 D10 D12 D13 D14 D15
ABS=1
D0
D3 D4 D5 D6 D7 D8 D9 D10 D11 Note : Internal X address : nH (REF="0") : 7FH-nH (REF="1")
* This specification is subject to be changed without notice.
39
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(2) Gradation mode (256 color), C256=1 8-bit mode(WLS=0) (REF, SWAP)=(0,0) or (1,1)
SEGAi SEGBi SEGCi
i=0 to 127
palette Aj
palette Bj
palette Cj
Gradation palette j=0 to 7
Gradation control
0 Gradation LSB circuit
0
0
M SB
1
LSB
0
0
M SB
1
LSB
1
1
M SB
display RAM data
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
MPU write data X address: nH
Note : Internal X address : nH : 7FH-nH
(REF="0") (REF="1")
(REF, SWAP)=(0,1) or (1,0)
SEGAi SEGBi SEGCi
i=0 to 127
Gradation palette
palette Cj
palette Bj
palette Aj
j=0 to 7
Gradation Control
0 Gradation LSB circuit
Display RAM data
1
M SB
1
1
LSB
0
M SB
0
1
LSB
0
M SB
0
MPU write data X address: nH
1 D0
1 D1
1 D2
0 D3
0 D4 (REF="1")
1 D5
0 D6
0 D7
Note : Internal X address : nH : 7FH-nH
(REF="0")
* This specification is subject to be changed without notice.
40
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
16-bit mode(WLS=1) (REF, SWAP)=(0,0) or (1,1)
SEGAi SEGBi SEGCi SEGAi+1 SEGBi+1 SEGCi+1
i=0, 2, 4 to 126
palette Aj
palette Bj
palette Cj
palette Aj
palette Bj
palette Cj
Gradation palette j=0 to 7
0 Gradation LSB circuit 0 0
M SB
1
LSB
0
0
M SB
1
LSB
1
1
MSB
0
0
M SB
1
LSB
0
0
M SB
1
LSB
1
1
M SB
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
0 D8
0 D9
1 D10
0 D11
0 D12
1 D13
1 D14
1 D15
MPU write data X address: nH
Note : Internal X address : nH : 3FH-nH
(REF="0") (REF="1")
(REF, SWAP)=(0,1) or (1,0)
SEGAi SEGBi SEGCi SEGAi+1 SEGBi+1 SEGCi+1
i=0, 2, 4 to 126
Gradation palette
palette Cj
palette Bj
palette Aj
palette Cj
palette Bj
palette Aj
j=0 to 7
Gradation control
0 1
M SB
display RAM data
1
1
LSB
0
M SB
0
1
LSB
0
M SB
0
1
MSB
1
1
LSB
0
M SB
0
1
LSB
0
M SB
0
Gradation LSB circuit
---------------
MPU write data X address: nH
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
0 D8
0 D9
1 D10
0 D11
0 D12
1 D13
1 D14
1 D15
Note : Internal X address : nH : 3FH-nH
(REF="0") (REF="1")
* This specification is subject to be changed without notice.
41
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(3)Monochrome mode In the monochrome mode, only three MSB in each display data are valid, the RAM mapping is the same gradation display mode.
8-bit mode
SEGAi
SEGBi
SEGCi
i=0 to 127
Monochrome control
1
LSB
1
1
0
M SB
1
LSB
1
1
0
M SB
1
LSB
1
1
0
M SB
display RAM data
0 D0
0 D1 D1 D1
0 D2 D2 D2
0 D4 D3 D3
0
0
0
0
0 D2 D4 D0
0 D3 D5 D1
0 D4 D6 D2
0 D7 D7 D3
D5 D6 D0 D1 D4 D5
D7 D1 D2 D3 D6 D7
MPU write data X address: 2nH,2n+1H
ABS=1 HSW=1
D0 D0
Note : Internal X address : 2nH ,2n+1H (REF="0") : (FE-2n)H , [FF-(2n+1)]H (REF="1") In HSW =1, Address=00H~BFH
16-bit mode
SEGAi SEGBi SEGCi
i=0 to 127
Monochrome control
1
LSB
1
1
0
M SB
1
LSB
1
1
0
M SB
1
LSB
1
1
0
M SB
display RAM data
0 D1
0 D2 D1
0 D3 D2
0 D4 D3
0
0
0
0
0 D8
0
0
0
MPU write data X address: nH
D7 D8 D4 D5
D9 D10 D12 D13 D14 D15 D6 D7 D9 D10 D11
ABS=1
D0
Note : Internal X address : nH (REF="0") : 7FH-nH (REF="1")
* This specification is subject to be changed without notice.
42
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.12 Gradation LSB Control In 256 color mode (C256=1), the EM65568 provides segment driver output for 8-gradation display using 3-bits and that for 4-gradation display using 2-bits. The segment driver output for the 4-gradation display uses 2-bits written to the corresponding RAM area and 1-bit supplemented by the gradation LSB circuit, and then selects 4-gradation form 8-gradation. In 256 color mode (C256=1), the segment driver output for the 4-gradation display result in a gradation level of 0 regardless of the gradation LSB, when 2-bits of data on the display RAM are "00". When 2-bits of data on the display RAM is "11",a gradation level of 7/7 is selected regardless of the bit information of the gradation LSB. The other gradation levels are selected depending on 2-bits of data on the display RAM and the gradation LSB bits. One bit of data is supplemented by setting the gradation LSB register (GLSB). The Gradation LSB control bit applied to all 4-gradation segment drivers. Gradation LSB = "0": Selects 0 as the LSB information on the RAM for 4-gradation segment drivers. Gradation LSB = "1": Selects 1 as the LSB information on the RAM for 4-gradation segment drivers. 7.13 Gradation Palette The EM65568 has two gradation display modes, the gradation fixed display mode and the gradation variable display mode. Select either of the two modes using the gradation display mode register. Caution: Different gradation levels can't be set the same palette. PWM = "0": Selects the variable display mode using 16 gradation selected from 32 gradation. (C256=0) Selects the variable display mode using 8 gradation selected from 32 gradation. (C256=1) PWM = "1": Selects the fixed display mode using specific 16 gradation. (C256=0) Selects the fixed display mode using specific 8 gradation. (C256=1) To select the best gradation level suited to the LCD panel, use the gradation palette register among the 32-level gradation palettes in the gradation variable display mode. The segment driver output is set up by the selected 16-levels of gradation palettes.
The gradation palette register provides three registers for the SEGAi (0-127) group, SEGBi (0-127) group, and SEGCi (0-127) group of segment driver outputs [palettes Aj, Bj, and Cj (j = 0-15)]. Each register consists of a 5-bit register, selecting 16-gradations from the pattern for 32-gradations.
* This specification is subject to be changed without notice.
43
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Initial values on gradation palette register Gradation mode (C256=0) [Three groups of palettes Aj, Bj, and Cj (j = 0-15) are available] (MSB)RAM data(LSB) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Register Name Initial value Palette0 00000 Palette1 00011 Palette2 00101 Palette3 00111 Palette4 01001 Palette5 01011 Palette6 01101 Palette7 01111 Palette8 10001 Palette9 10011 Palette10 10101 Palette11 10111 Palette12 11001 Palette13 11011 Palette14 11101 Palette15 11111
256 color mode (C256=1) [Three groups of palettes Aj, Bj, and Cj (j = 0-7) are available] (MSB)RAM data(LSB) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Register Name Palette0 Palette1 Palette2 Palette3 Palette4 Palette5 Palette6 Palette7 Initial value 00000 00101 01010 01110 10001 10101 11010 11111
* This specification is subject to be changed without notice.
44
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Gradation level table (PWM = "0", variable mode , MON= "0") [Three groups of palettes Aj, Bj, and Cj (j = 0-15) are available
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Gradation level 0 1/31 2/31 3/31 4/31 5/31 6/31 7//31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Remarks gradation palette0 initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Palette 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Remarks gradation palette8 initial value gradation palette9 initial value gradation palette10 initial value gradation palette11 initial value gradation palette12 initial value gradation palette13 initial value gradation palette14 initial value gradation palette15 initial value
gradation palette1 initial value gradation palette2 initial value gradation palette3 initial value gradation palette4 initial value gradation palette5 initial value gradation palette6 initial value gradation palette7 initial value
256 color mode (C256=1) [Three groups of palettes Aj, Bj, and Cj (j = 0-7) are available
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Gradation level 0 1/31 2/31 3/31 4/31 5/31 6/31 7//31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Remarks 256 color palette0 initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Palette 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Remarks 256 color palette4 initial value
256 color palette1 initial value
256 color palette5 initial value
256 color palette2 initial value
256 color palette6 initial value
256 color palette3 initial value
256 color palette7 initial value
* This specification is subject to be changed without notice.
45
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Gradation level table (PWM = "1", fixed mode , MON= "0", C256= "0") (MSB)RAM data(LSB) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Gradation Level 0 1/15 2/15 3/15 4/15 5/15 6/15 7/15 8/15 9/15 10/15 11/15 12/15 13/15 14/15 15/15
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Gradation level table (PWM = "1", fixed mode , MON= "0", C256= "1") (MSB)RAM data(LSB) 0 0 * 0 1 * 1 0 * 1 1 * 0 0 * 0 1 * 1 0 * 1 1 * Gradation Level 0 1/7 2/7 3/7 4/7 5/7 6/7 7/7
0 0 0 0 1 1 1 1
Monochrome mode , MON= "1" 0 1 (MSB)RAM data(LSB) * * * * * * Gradation Level 0 1
*: don't care
* This specification is subject to be changed without notice.
46
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.14 Display Timing Circuit The display timing circuit generates internal signals and timing pulses (LP, FLM, M and CLK) by clock. It can select external input (CK) or internal oscillation. By setting up Master/Slave mode (M/S), the state of timing pulse pins and the timing generator changes.
M/S Pin Mode LP Pin M Pin FLM Pin CLK Pin L Slave Input Input Input Input H Master Output Output Output Output State of timing generator LP,FLM,M generation stop Operation state
Display timing pulse pins and Generator State 7.15 Signal Generation to Display Line Counter, and Display Data Latching Circuit Both the clock to the line counter and clock to display data latching circuit from the display clock (LP) are generated. Synchronized with the display clock (LP), the line addresses of Display RAM are generated and 384-bits display data are latched to display data latching circuit to output to the LCD drive circuit (Segment outputs). Read-out of the display data to the LCD drive circuit is completely independent of MPU. Therefore, MPU that has no relationship the read-out operation of the display data can access.
7.16 Generation of the Alternated Signal (M) and the Synchronous Signal (FLM) LCD alternated signal (M) and synchronous signal (FLM) are generated by the display clock (LP). The FLM generates alternated drive waveform to the LCD drive circuit. Normally, the FLM generates alternated drive waveform every frame (M-signal level is reversed every one frame). However, by setting up data (n-1) in an n-line reverse register and n-line alternated control bit (NLIN) at "1", n-line reverse waveform is generated. When the EM65568 is used in multi chip system, master chip must provide LP, FLM, and M signals for the slave chip.
7.17 Display Data Latching Circuit Display data latching Circuit temporally latches display data that is output display data to LCD driver circuit from display RAM every one common period. Normal display/reverse display, display ON/OFF, and display all on functions are operated by controlling data in display data latch. Therefore, no data within display RAM changes.
* This specification is subject to be changed without notice.
47
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.18 Output Timing of LCD Driver Display timing at Normal mode (not reverse mode), 1/130 DUTY, and on monochrome mode. 129 LP FLM M V0 V1 COM0 V4 VSS V0 V1 COM1 V4 VSS V0 V2 SEG0 V3 VSS V0 V2 SEG1 V3 V2 V3 VSS V3 V2 V3 V0 V4 V1 V1 V4 VSS 130 1 2 3 130 1 2 3 130 1
* This specification is subject to be changed without notice.
48
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.19 LCD Drive Circuit This drive circuit generates four levels LCD drive voltage. The circuit has 384 segment outputs and 130 common outputs and outputs combined display data and M signal. Two of common outputs, COMA and COMB, are special outputs. The COMA and COMB outputs be not influenced by partial setting. Mainly use for display. The common drive circuit that has shift register sequentially outputs common scan signals.
7.20 Oscillating Circuit The EM65568 has the CR oscillator. The output from this oscillator is used as the timing signal source of the display and the boosting clock to the booster. This can use only in the master operation mode. When in the master operation mode and external clock is used, feed the clock to CK pin. The duty cycle of the external clock must be 50%. The resistance ratio of CR oscillator is programmable. If change this ratio, also change frame frequency for display. 7.21 Power Supply Circuit This circuit supplies voltages necessary to drive a LCD. The circuit consists of booster and voltage converter. Boosted voltage from the booster is fed to the voltage converter that converts this input voltage into V0, V1, V2, V3 and V4 that are used to drive the LCD. This internal power supply should not be used to drive a large LCD panel containing many pixels. Otherwise, display quality will degrade considerably. Instead, use an external power supply. When using the external power supply, turn off the internal power supply (AMPON, DCON="00"), disconnect pins CAP1+, CAP2+, CAP2-, CAP3+, CAP3-, CAP4+, CAP4-, CAP5+, CAP5-,VOUT, VEE, VREF and VREG. Then, feed external LCD drive voltages to pins V0, V1, V2, V3 and V4. The power circuit can be control by power circuit related register. So partial function of built-in power circuit can use with external power supply.
DCON AMPON Booster circuit Voltage conversion circuit 0 0 1 0 1 1 DISABLE DISABLE ENABLE DISABLE ENABLE ENABLE Extemal voltage input V0,V1,V2,V3 and V4 are supplied VOUT is supplied Note 1 2 -
1 Because the booster and voltage converter not operating, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP3-, CAP4+, CAP4 -, CAP5+, CAP5-, VOUT, VREF, VREG and VEE. Apply external LCD drive voltages to corresponding pin. 2 Because the booster is not operating, disconnect pins CAP1+, CAP1-, CAP2+, CPA2-, CAP3+, CAP3-, CAP4+, CAP4-, CAP5+, CAP5- and VEE. Derive the voltage source to be supplied to the voltage converter from VOUT pin and then Input the reference voltage at VREF pin.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.22 Booster Circuit Placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3-, across CAP4+ and CAP4-, across CAP5+ and CAP5-and across VOUT and VSS boosts the voltage coming from VEE and VSS n-times and outputs the boosted voltage to VOUT pin. The twice, third, fourth or fifth boosted voltage output to the VOUT pin by the boost step register set. The boost step registers set by the command. (1) In case of using only twice boosted voltage, placing C1 only across CAP1+ and CAP1- and opening CAP2+, CAP2-, CAP3+, CAP3-, CAP4+, CAP4-, CAP5+ and CAP5-. (2) In case of using only third boosted voltage, placing C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2- and opening CAP3+, CAP3-, CAP4+, CAP4, CAP5+ and CAP5-. (3) In case of using only fourth boosted voltage, placing C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3- and opening CAP4+, CAP4, CAP5+ and CAP5. (4) In case of using only fifth boosted voltage, placing C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3- across CAP4+ and CAP4- and opening CAP5+ and CAP5. (5) In case of using only sixth boosted voltage, placing C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3- across CAP4+ and CAP4- across CAP5+ and CAP5. When use built-in booster circuit, output voltage (VOUT) must less than recommended operating voltage (18.0 Volt). If output voltage (VOUT) over recommended operating voltage, correct work of chip can not guarantee. VOUT=9V VOUT=18V
VEE=3V VSS=0V 3 times boosting
VEE=3V VSS=0V 6 times boosting
* This specification is subject to be changed without notice.
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7.23 Electronic volume The voltage conversion circuit has built-in an electronic volume, which allows the LCD drive voltage level V0 to be controlled with DV register setting and allows the tone of LCD to be controlled. The DV registers are 7-bits, so can select 128 voltage values for the LCD drive voltage V0.
7.24 Voltage Regulator The EM65568 has built-in reference voltage regulator, which generate the voltage amplified by input voltage from VREF pin. The generated voltage is output at the VREG pin. Even if the boosted voltage level fluctuates, VREG remains stable so far as VOUT is higher than VREG Stable power supply can be obtained using this constant voltage, even if the load fluctuates. The EM65568 uses the generated VREG level for the reference level of the electronic volume to generate LCD drive voltage. In order to stabilize the output voltage at the VREG pin, connect the capacitor C3 as appropriate by choosing its value.
7.25 0.9 times VDD Voltage Generation Circuit The EM65568 has 0.9 times VDD voltage generation circuit. This circuit output 0.9 times VDD voltage from VBA pin. When VBA output connect to VREF input, LCD drive voltage can generate without external reference voltage.
7.26 LCD Drive Voltage Generation Circuit The voltage converter contains the voltage generation circuit. The LCD drive voltages other than V0, that is, V1, V2, V3 and V4 are obtained by dividing V0 through a resistor network. The LCD drive voltage from EM65568 is biased at 1/5, 1/6, 1/7, 1/8 , 1/9, 1/10, 1/11 or 1/12. When using the internal power supply, connect a stabilizing capacitor C2 to each of pins V0 to V4. The capacitance of C2 should be determined while observing the LCD panel to be used. When using the external power supply, apply external LCD drive voltages to V0, V1, V2, V3, V4, disconnect pins CAP1+, CAP-, CAP2+, CAP2-, CAP3+, CAP3-, CAP4+, CAP4-, CAP5+, CAP5-, VOUT, VEE, VREF and VREG. When using only the voltage conversion circuit, turn off the internal booster circuit, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP3-, CAP4+, CAP4- CAP5+, CAP5- and VEE. Derive the voltage source to be supplied to the voltage converter from VOUT pin and then input the reference voltage to VREF pin.
* This specification is subject to be changed without notice.
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VDD VDD VEE VBA VREF VREG CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ CAP4CAP4+ CAP5+ CAP5Vout V0 External V1 Power V2 Supply V3 V4 VOUT V0 V1 V2 V3 V4 vss vss C3
VDD VDD VEE VBA VREF VREG C1 C1 C1 C1 C1 C1 vss C2 C2 C2 C2 C2 VOUT V0 V1 V2 V3 V4 CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ CAP4CAP4+ CAP5+ CAP5-
When using external power supply.
When using internal power circuit. (6 times boosting)
Recommended value.
C1 C2 C3
1.0 to 4.7 Uf 1.0 to 2.2 Uf 0.1 Uf
Note: External Capacitance must be use B characteristic.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
VDD VDD VEE VBA VREF VREG C3 vss C1 C1 C1 C1 C1 vss C2 C2 C2 vss C2 C2 VOUT V0 V1 V2 V3 V4 vss vss C1 CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ CAP4CAP4+ CAP5CAP5+
Thermistor
VDD VDD VEE VBA VREF VREG C3 vss C1 C1 C1 C1 C1 VOUT C2 C2 C2 C2 C2 V0 V1 V2 V3 V4 C1 CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ CAP4CAP4+ CAP5CAP5-
When using internal power circuit with external reference voltage input. (6 times boosting)
When using internal power circuit with thermistor for temperature independent. (6 times boosting)
Recommended value.
C1 C2 C3
1.0 to 4.7 Uf 1.0 to 2.2 Uf 0.1 Uf
Note: External Capacitance must be use B characteristic.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
VDD VDD VEE VBA C3 vss VREF VREG CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ CAP4CAP4+ CAP5CAP5+ External Power Supply C2 C2 C2 C2 C2 VOUT V0 V1 V2 V3 V4
vss
When using internal power circuit. (VOUT supplied from external, no use boosting circuit) Recommended value.
C2 C3
1.0 to 2.2 Uf 0.1 Uf
Note: External Capacitance must be use B characteristic.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.27 Partial Display Function The EM65568 has the partial display function, which can display a part of graphic display area. This function is used be set lower bias ratio, lower boost step, and lower LCD drive voltage. Since setting partial display function, EM65568 provides low power consumption. Partial display function is the most suitable for clock indication or calendar indication when a portable equipment stand-by.
ELAN LCD DRIVER Low Power and Low Voltage Normal Display Partial Display LCD DRIVER
Image of partial Display When using the partial display function, it is necessary to keep following sequence.
Any display condition Display off (ON/OFF= "0") Power circuit off (DCON= "0", AMPON= "0") W AIT
Setting Power Function * Boost step set * Electronic volume set * Bias Ratio set
Power circuit on (DCON= "1", AM PON= "1") W AIT
Setting Display Function * Duty Ratio set * Display start Address * Display start common
Display on (ON/OFF= "1") Partial Display
* This specification is subject to be changed without notice.
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Select a display duty ratio for the partial display from 1/10 to 1/130 using the DS(Lcd duty ratio) register. Set the most suitable values for LCD drive bias ratio, LCD drive voltage, electronic volume, the number of boosting steps, and others according to the actually used LCD panel and the selected duty ratio. 7.28 Discharge circuit The EM65568 has built-in the discharge circuit, which discharges electricity from capacitors for a stability of power sources (V0~V4). The discharge circuit is valid, while the DIS register is set to "1". When the built-in power supply is used, should be set DIS="1" after the power source is turned off (DCON, AMPON)=(0, 0). And don't turn on both the built-in power source and the external power source (V0~V4, VOUT) while DIS="1".
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.29 Initialization The EM65568 is initialized by setting RESB pin to "L". Normally, RESB pin is initialized together with MPU by connecting to the reset pin of MPU. When power ON, be sure to make RESB="L". 4096 color mode ITEM Display RAM X Address Y Address Display starting line Display ON/OFF Display Normal/Reverse Display duty n-line alternated (BF1,BF0) Common shift direction Increment mode REF mode Data SWAP Mode Register in electronic volume Power Supply Display mode Bias ratio Gradation palette 0 Gradation palette 1 Gradation palette 2 Gradation palette 3 Gradation palette 4 Gradation palette 5 Gradation palette 6 Gradation palette 7 Gradation palette 8 Gradation palette 9 Gradation palette 10 Gradation palette 11 Gradation palette 12 Gradation palette 13 Gradation palette 14 Gradation palette 15 Gradation display mode Gradation LSB RAM access data length Discharge Register Initial value Not fixed 00H set 00H set Set at the first line(0H) Display OFF Normal 1/10 every frame unit (0,0) COM0 COM127, COMA, COMB Increment OFF Normal OFF (0,0,0,0,0,0,0) OFF Gradation display mode 1/5 bias (0, 0, 0, 0, 0) (0, 0, 0, 1, 1) (0, 0, 1, 0, 1) (0, 0, 1, 1, 1) (0, 1, 0, 0, 1) (0, 1, 0, 1, 1) (0, 1, 1, 0, 1) (0, 1, 1, 1, 0) (1, 0, 0, 0, 1) (1, 0, 0, 1, 1) (1, 0, 1, 0, 1) (1, 0, 1, 1, 1) (1, 1, 0, 0, 1) (1, 1, 0, 1, 1) (1, 1, 1, 0, 1) (1, 1, 1, 1, 1) Variable mode 0 8-bits mode 0
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
7.30 Precaution when Power ON and Power OFF This LSI may be permanently damaged by high current that may flow if a voltage is supplied to the LCD driver power supply while the system power supply is floating. The detail is as follows.
( i )When using as external power supply Procedure for Power ON (1) Logic system (VDD) power ON, make reset operation. (2) Supply external LCD drive voltage to corresponding pins (V0, V1, V2, V3 and V4) Procedure for Power OFF (1) Set HALT register to "1" or make reset operation. (2) Cut off external LCD drive voltage. (3) Logic system(VDD) power OFF. Note: connect the serial resistor (50 to 100) or fuse to the LCD drive power V0 or VOUT(when only use internal voltage conversion circuit) of the system as a current limiter. Moreover, set up the suitable value of the resistor in consideration of LCD display grade. ( ii )When using the built-in power supply Procedure for Power ON (1) Logic system(VDD) power ON (2) Booster circuit system(VEE) power ON (3) Make reset operation, booster and voltage conversion circuit enable. If VDD and VEE voltages aren't same potential, power on logic system (VDD) first. Procedure for Power OFF (1) Set HALT register to "1" or make reset operation. (2) Booster circuit system(VEE) power OFF. (3) Logic system(VDD) power OFF. If VDD and VEE are not same potential, cut off VEE first. After VEE, VOUT, V0, V1, V2, V3 and V4 voltages are below LCD ON voltage (threshold voltage for Liquid crystal turn on), power off logic system (VDD).
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
( iii )Power supply rising time Though especially there is no constraint on the rising time of the power supply, the tr (rising time) of the following is recommended in the practical use.
VDD,VEE tr
Item tr
Recommended rising time 30us ~ 10ms
Applicable Power VDD, VEE
Note: The rising time is the time from 10% of VDD,VEE to 90%. 7.31 Example of Setting Registers (1) Initialization
Power ON (VDD,VEE-VSS) Power will stable RESET W AIT
Setting Operational Functions * Electrical volume set * Bias Ratio set
Setting Operational Functions * Setting power control (DCON= "1", AMPON= "1")
End of initialization
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(2) Display data
End of initialization
* * * *
Setting Operational Functions Setting display start address Setting address increment control Setting X address Setting Y address
Setting Operational Functions * W rite dsiplay data
Setting Operational Functions * Setting display on/off control (ON/OFF= "1")
End of display data setting
(3) Power OFF
Any condition
Setting Operational Functions * Setting HALT= "1" or make reset operation (LCD driver output VSS level) * Setting DIS= "1" (Discharge V0-V4 capacitor)
W AIT
Power OFF ( VEE,VDD)
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
8. Control Register
8.1 control register Control Register Table (Bank 0)
Control Register X Address (Lower nibble) X Address (Upper nibble) Y Address (Lower nibble) Y Address (Upper nibble) Display start address (Lower nibble) Display start address (Upper nibble) n-line altemation (Lower nibble) n-line altemation (Upper nibble) Display control (1) [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] Pins (for 80-family) & Bank Address & Code D2 AX2 AX6 AY2 AY6 LA2 LA6 N2 N6 D1 AX1 AX5 AY1 AY5 LA1 LA5 N1 N5 Function Set of X direction Address AX0 in display RAM Set of X direction Address AX4 in display RAM Set of Y direction Address AY0 in display RAM Set of Y direction Address AY4 in display RAM Set address of display RAM LA0 making common starting line display Set address of display RAM LA4 making common starting line display Set the number of altemated N0 reverse line Set the number of altemated N4 reverse line SHIFT: Select common shift direction MON: Select Monochrome/gradation ON/ ALLON: All display ON OFF ON/OFF: Display ON/OFF control REV: Display normal/reverse NLIN: n line reverse control SWAP: Display data swapping REF REF: Seqment normal/reverse WIN: Select window. AIM: Select increment mode AXI AYI: Y increment, AXI: X increment AMPON: Internal AMP. ON HALT: Power saving DCON: Boosting circuit ON ACL ACL: Resetting Set LCD drive duty ratio DS0 Set number of boosting step for VU0 booster circuit Set bias ratio B0 for LCD driving voltage TST0: for LS1 test,must set to "0" RE0 RE: set register bank number D0 CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 AX3 1 AX7 0 AY3 1 AY7 0 LA3 1* 0 N3 1 N7
[8H] Display control (2)
0
1
0
1
0
0
0
1
0
0
SHI 0 FT
ALL MON ON
[9H] Increment control [AH] Power control
0
1
0
1
0
0
0
1
0
0
SW 1 REV NLIN AP
0
1
0
1
0
0
0
1
0
1
0 WIN AIM
AYI
[BH] LCD Duty Ratio [CH] Booster [DH] Bias ratio control [EH] Register Access Control [FH]
0 0 0 0 0
1 1 1 1 1
0 0 0 0 0
1 1 1 1 1 0/1
0 0 0 0 0/1
0 0 0 0 0/1
0 0 0 0
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
AMP HA 1 ON LT 0 DS3 DS2 1* 0* TS 1 T0 VU2 B2 RE2
DC ON DS1 VU1 B1 RE1
Note: The "" mark means "don't care" Parentheses [ ] shows address for control register.
* This specification is subject to be changed without notice.
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Control Register Table (Bank 1)
Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 Gradation palette A0 PA03 PA02 PA01 PA00 (Lower nibble) [0H] 01 0 1 0 0 1 0 0 0 0 /PA83 /PA82 /PA81 /PA80 Gradation palette A0 PA04 (Upper nibble) [1H] 01 0 1 0 0 1 0 0 0 1* * * /PA84 Gradation palette A1 PA13 PA12 PA11 PA10 (Lower nibble) [2H] 01 0 1 0 0 1 0 0 1 0 /PA93 /PA92 /PA91 /PA90 Gradation palette A1 PA14 (Upper nibble) [3H] 01 0 1 0 0 1 0 0 1 1* * * /PA94 Gradation palette A2 PA23 PA22 PA21 PA20 (Lower nibble) [4H] 01 0 1 0 0 1 0 1 0 0 /PA103 /PA102 /PA101 /PA100 Gradation palette A2 PA24 (Upper nibble) [5H] 01 0 1 0 0 1 0 1 0 1* * * PA104 Gradation palette A3 PA33 PA32 PA31 PA30 (Lower nibble) [6H] 01 0 1 0 0 1 0 1 1 0 /PA113 /PA112 /PA111 /PA110 Gradation palette A3 PA34 (Upper nibble) [7H] 01 0 1 0 0 1 0 1 1 1* * * PA114 Gradation palette A4 PA43 PA42 PA41 PA40 (Lower nibble) [8H] 01 0 1 0 0 1 1 0 0 0 /PA123 /PA122 /PA121 /PA120 Gradation palette A4 PA44 (Upper nibble) [9H] 01 0 1 0 0 1 1 0 0 1* * * PA124 Gradation palette A5 PA53 PA52 PA51 PA50 (Lower nibble) [AH] 01 0 1 0 0 1 1 0 1 0 /PA133 /PA132 /PA131 /PA130 Gradation palette A5 PA54 (Upper nibble) [BH] 01 0 1 0 0 1 1 0 1 1* * * PA134 Gradation palette A6 PA63 PA62 PA61 PA60 (Lower nibble) [CH] 01 0 1 0 0 1 1 1 0 0 /PA143 /PA142 /PA141 /PA140 Gradation palette A6 PA64 (Upper nibble) [DH] 01 0 1 0 0 1 1 1 0 1* * * /PA144 TS Register Access Control [FH] 01 0 1 0/1 0/1 0/1 1 1 1 1 T0 RE2 RE1 RE0 Control Register Function Set the umber of Gradation Palette A0 Set the umber of Gradation Palette A0 Set the umber of Gradation Palette A1 Set the umber of Gradation Palette A1 Set the umber of Gradation Palette A2 Set the umber of Gradation Palette A2 Set the umber of Gradation Palette A3 Set the umber of Gradation Palette A3 Set the umber of Gradation Palette A4 Set the umber of Gradation Palette A4 Set the umber of Gradation Palette A5 Set the umber of Gradation Palette A5 Set the umber of Gradation Palette A6 Set the umber of Gradation Palette A6 TST0: for LS1 test,must set to "0 RE: set register bank number
Note: The "" mark means "don't care" Parentheses [ ] shows address for control register.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Control Register Table (Bank 2)
Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 Gradation palette A7 PA73 PA72 PA71 PA70 (Lower nibble) [0H] 01 0 1 0 1 0 0 0 0 0 /PA153 /PA152 /PA151 /PA150 Gradation palette A7 PA74 (Upper nibble) [1H] 01 0 1 0 1 0 0 0 0 1* * * /PA154 Gradation palette B0 PB03 PB02 PB01 PB00 (Lower nibble) [2H] 01 0 1 0 1 0 0 0 1 0 /PB83 /PB82 /PB81 /PB80 Gradation palette B0 PB04 (Upper nibble) [3H] 01 0 1 0 1 0 0 0 1 1* * * /PB84 Gradation palette B1 PB13 PB12 PB11 PB10 (Lower nibble) [4H] 01 0 1 0 1 0 0 1 0 0 PB93 PB92 PB91 PB90 Gradation palette B1 PB14 (Upper nibble) [5H] 01 0 1 0 1 0 0 1 0 1* * * PB94 Gradation palette B2 PB23 PB22 PB21 PB20 (Lower nibble) [6H] 01 0 1 0 1 0 0 1 1 0 PB103 PB102 PB101 PB100 Gradation palette B2 PB24 (Upper nibble) [7H] 01 0 1 0 1 0 0 1 1 1* * * PB104 Gradation palette B3 PB33 PB32 PB31 PB30 (Lower nibble) [8H] 01 0 1 0 1 0 1 0 0 0 PB113 PB112 PB111 PB110 Gradation palette B3 PB34 (Upper nibble) [9H] 01 0 1 0 1 0 1 0 0 1* * * PB114 Gradation palette B4 PB43 PB42 PB41 PB40 (Lower nibble) [AH] 01 0 1 0 1 0 1 0 1 0 PB123 PB122 PB121 PB120 Gradation palette B4 PB44 (Upper nibble) [BH] 01 0 1 0 1 0 1 0 1 1* * * PB124 Gradation palette B5 PB53 PB52 PB51 PB50 (Lower nibble) [CH] 01 0 1 0 1 0 1 1 0 0 PB133 PB132 PB131 PB130 Gradation palette B5 PB54 (Upper nibble) [DH] 01 0 1 0 1 0 1 1 0 1* * * PB134 Register Access Control TS [FH] 01 0 1 0/1 0/1 0/1 1 1 1 1 T0 RE2 RE1 RE0 Control Register Function Set the umber of Gradation Palette A7 Set the umber of Gradation Palette A7 Set the umber of Gradation Palette B0 Set the umber of Gradation Palette B0 Set the umber of Gradation Palette B1 Set the umber of Gradation Palette B1 Set the umber of Gradation Palette B2 Set the umber of Gradation Palette B2 Set the umber of Gradation Palette B3 Set the umber of Gradation Palette B3 Set the umber of Gradation Palette B4 Set the umber of Gradation Palette B4 Set the umber of Gradation Palette B5 Set the umber of Gradation Palette B5 TST0: for LS1 test,must set to "0 RE: set register bank number
Note: The "" mark means "don't care" Parentheses [ ] shows address for control register.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Control Register Table (Bank 3)
Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 Gradation palette B6 PB63 PB62 PB61 PB60 (Lower nibble) [0H] 01 0 1 0 1 1 0 0 0 0 /PB143 /PB142 /PB141 /PB140 Gradation palette B6 PB64 (Upper nibble) [1H] 01 0 1 0 1 1 0 0 0 1* * * /PB144 Gradation palette B7 PB73 PB72 PB71 PB70 (Lower nibble) [2H] 01 0 1 0 1 1 0 0 1 0 /PB153 /PB152 /PB151 /PB150 Gradation palette B7 PB74 (Upper nibble) [3H] 01 0 1 0 1 1 0 0 1 1* * * /PB154 Gradation palette C0 PC03 PC02 PC01 PC00 (Lower nibble) [4H] 01 0 1 0 1 1 0 1 0 0 /PC83 /PC82 /PC81 /PC80 Gradation palette C0 PC04 (Upper nibble) [5H] 01 0 1 0 1 1 0 1 0 1* * * /PC84 Gradation palette C1 PC13 PC12 PC11 PC10 (Lower nibble) [6H] 01 0 1 0 1 1 0 1 1 0 /PC93 /PC92 /PC91 /PC90 Gradation palette C1 PB14 (Upper nibble) [7H] 01 0 1 0 1 1 0 1 1 1* * * /PC94 Gradation palette C2 PC23 PC22 PC21 PC20 (Lower nibble) [8H] 01 0 1 0 1 1 1 0 0 0 /PC103 /PC102 /PC101 /PC100 Gradation palette C2 PB24 (Upper nibble) [9H] 01 0 1 0 1 1 1 0 0 1* * * /PC104 Gradation palette C3 PC33 PC32 PC31 PC30 (Lower nibble) [AH] 01 0 1 0 1 1 1 0 1 0 /PC113 /PC112 /PC111 /PC110 Gradation palette C3 PB34 (Upper nibble) [BH] 01 0 1 0 1 1 1 0 1 1* * * /PC114 Gradation palette C4 PC43 PC42 PC41 PC40 (Lower nibble) [CH] 01 0 1 0 1 1 1 1 0 0 /PC123 /PC122 /PC121 /PC120 Gradation palette C4 PB44 (Upper nibble) [DH] 01 0 1 0 1 1 1 1 0 1* * * /PC124 Register Access Control TS [FH] 01 0 1 0/1 0/1 0/1 1 1 1 1 T0 RE2 RE1 RE0 Control Register Function Set the umber of Gradation Palette B6 Set the umber of Gradation Palette B6 Set the umber of Gradation Palette B7 Set the umber of Gradation Palette B7 Set the umber of Gradation Palette C0 Set the umber of Gradation Palette C0 Set the umber of Gradation Palette C1 Set the umber of Gradation Palette C1 Set the umber of Gradation Palette C2 Set the umber of Gradation Palette C2 Set the umber of Gradation Palette C3 Set the umber of Gradation Palette C3 Set the umber of Gradation Palette C4 Set the umber of Gradation Palette C4 TST0: for LS1 test,must set to "0 RE: set register bank number
Note: The "" mark means "don't care" Parentheses [ ] shows address for control register.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Control Register Table (Bank 4)
Control Register Gradation palette C5 (Lower nibble) Gradation palette C5 (Upper nibble) Gradation palette C6 (Lower nibble) Gradation palette C6 (Upper nibble) Gradation palette C7 (Lower nibble) Gradation palette C7 (Upper nibble) Display start common Display Select Control [8H] RAM Data length Set [9H] Electronic Volume (Lower nibble) Electronic Volume (Upper nibble) Register read Control Select Rf [DH] Extended Power Control [EH] Register Access Control [FH] 0 1 0 1 0/1 0/1 0/1 1 1 1 0 1 0 1 1 0 0 1 1 1 0 BF1 TS 1 T0 BF0 RE2 HPM RE1 DIS RE0 0 1 0 1 1 0 0 1 1 0 1* RF2 RF1 RF0 Discharge capacitance of V0,V1,V2,V3,V4 Pins TST0: for LS1 test,must set to "0" RE: set register bank number [AH] [BH] [CH] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 C256 0 DV3 1* 0 RA3 HSW DV2 DV6 RA2 ABS DV1 DV5 RA1 WLS DV0 DV4 RA0 Select Rf ratio of OSC circuit 0 1 0 1 1 0 0 1 0 0 0 PWM [0H] [1H] [2H] [3H] [4H] [5H] [6H] Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 PC53 PC52 C51 PC50 0 1 0 1 1 0 0 0 0 0 0 /PC133 /PC132 /PC131 /PC130 PC54 0 1 0 1 1 0 0 0 0 0 1* * * /PC134 PC63 PC62 PC61 PC60 0 1 0 1 1 0 0 0 0 1 0 /PC143 /PC142 /PC141 /PC140 PC64 0 1 0 1 1 0 0 0 0 1 1* * * /PC144 PC73 PC72 PC71 PC70 0 1 0 1 1 0 0 0 1 0 0 /PC153 /PC152 /PC151 /PC150 PC74 0 1 0 1 1 0 0 0 1 0 1* * * /PC154 0 1 0 1 1 0 0 0 1 1 0 SC3 SC2 GL SB SC1 SC0 PS Function Set the umber of Gradation Palette C5 Set the umber of Gradation Palette C5 Set the umber of Gradation Palette C6 Set the umber of Gradation Palette C6 Set the umber of Gradation Palette C7 Set the umber of Gradation Palette C7 Set Common Driver Start Line Select Plane(access/display) Set GLSB Bit. Select PWM Mode Set Data length on RAM Access 8-bit access or 16-bit access Set Electronic Vollume Register (lower code) Set Electronic Vollume Register (upper code) Set Register Address for read
Note: The "" mark means "don't care" Parentheses [ ] shows address for control register.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Control Register Table (Bank 5)
Control Register Window X End Address (Lower nibble) Window X End Address (Upper nibble) Window Y End Address (Lower nibble) Window Y End Address (Upper nibble) Start Address for line reverse (Lower nibble) Start Address for line reverse (Upper nibble) End Address for line reverse (Lower nibble) End Address for line reverse (Upper nibble) Line reverse control Register Access Control [FH] 0 1 0 1 0/1 0/1 0/1 1 1 1 [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] CSB 0 0 0 0 0 0 0 0 0 Pins (for 80-family) & Bank RS WRB RDB RE2 RE1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 RE0 1 1 1 1 1 1 1 1 1 D7 0 0 0 0 0 0 0 0 1 D6 0 0 0 0 1 1 1 1 0 D5 0 0 1 1 0 0 1 1 0 Address & Code D4 D3 D2 D1 0 EX3 1 EX7 0 EY3 1 EY7 0 LS3 1 LS7 0 LE3 1 LE7 0* TS 1 T0 EX2 EX6 EY2 EY6 LS2 LS6 LE2 LE6 * RE2 EX1 EX5 EY1 EY5 LS1 LS5 LE1 LE5 BT RE1 D0 EX0 EX4 EY0 EY4 LS0 Set start line for line reverse display LS4 Set end line for line reverse display LE0 Set end line for line reverse display LE4 LR EV RE0 LREV: Line reverse control BT: Reverse type select TST0: for LS1 test,must set to "0" RE: set register bank number Function Set X end address for window function access Set X end address for window function access Set Y end address for window function access Set Y end address for window function access Set start line for line reverse display
Note: The "" mark means "don't care" Parentheses [ ] shows address for control register.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
8.2 Functions of Control Registers The EM65568 has many control registers as shown in "7 Control Register". In case of control register access, upper nibble of data bus(D7~D4) represent register address, lower nibble of data bus(D3~D0) represent data. The access example is shown in the following. The Pins (CSB, RS, RDB, WRB) setting are for 80-family MPU interface. Only the setting of terminal (RDB,WRB) is different, when it is accessed by the 68-fanily MPU. (Example) X Address
D7 0 D6 0 D5 0 D4 0 D3 AX3 D2 AX2 D1 AX1 D0 AX0 CSB 0 RS 1 RDB 1 WRB 0 RE2 0 RE1 0 RE0 0
Register address
Data
Pins setting
Register Bank
In the writing to the control register, it is used directly as addressing D7~D4 of the data bus. In case of register read, first set RA register for specific register address, next can read specific register. Therefore, it is need 2-step for register read. Then, specific register output to D3~D0 of data bus. Except D3~D0 of data bus are all "H". Prohibit access to undefined register address area. When RS is "L", all read/write operations are accessed to display RAM. Then data bus doesn't include register address. In case of write, D3~D0 data is written to the register designated at D7~D4 in rising edge of the WRB signal. In case of read, register can output to data bus is RDB active period. Control register and display RAM are the equal access timing.
8.2.1 X Address Register (AX)
D7 0 D6 0 D5 0 D4 0 D3 AX3 D2 AX2 D1 AX1 D0 AX0 CSB 0 RS 1 RDB WRB 1 0 RE2 0 RE1 0 RE0 0
(At the time of reset: {AX3, AX2, AX1, AX0}= 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 AX7 D2 AX6 D1 AX5 D0 AX4 CSB 0 RS 1 RDB WRB 1 0 RE2 0 RE1 0 RE0 0
(At the time of reset: {AX7, AX6, AX5, AX4}= 0H, read address: 1H) The AX register set to X-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit and 4-bit respectively. 8.2.2 Y Address Register D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 AY3 AX2 AY1 AY0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {AY3, AY2, AY1, AY0}=0H, read address: 2H) D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 AY7 AY6 AY5 AY4 CSB 0 67 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 2005/3/8 (V1.2)
* This specification is subject to be changed without notice.
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(At the time of reset: {AY7, AY6, AY5, AY4}=0H, read address: 3H) Mark shows "Don't care" The AY register set to Y-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit and 4-bit respectively. 00H to 81H are applicable to the values for AY7 to AY0, and 82H to FFH are not permitted. The address for (AY7 to AY0) = 70H, 81H are in the display RAM area for icon display.
8.2.3 Display Start Address Register (LA) D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 LA3 LA2 LA1 LA0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {LA3, LA2, LA1, LA0}=0H, read address: 4H) D7 0 D6 1 D5 0 D4 1 D3 D2 D1 D0 LA6 LA5 LA4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: { LA6, LA5, LA4}=0H, read address: 5H) Mark shows "Don't care" The LA register indicated first output segment data in display RAM. This segment data output to common line indicated by SC register. After that output common line shift to the increment direction.
LA6 0 0 1
LA5 0 0 1
LA4 0 0 1
LA3 0 0 1
LA2 0 0 1
LA1 0 0 1
LA0 0 1 1
Line Address 0 1 127
8.2.4 n Line Alternated Register (N) D7 0 D6 1 D5 1 D4 0 D3 N3 D2 N2 D1 N1 D0 N0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {N3, N2, N1, N0}=0H, read address: 6H) D7 0 D6 1 D5 1 D4 1 D3 N7 D2 N6 D1 N5 D0 N4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {N7,N6, N5, N4}=0H, read address: 7H) Mark shows "Don't care"
The reverse line number of LCD alternated drive is required to set in the register. The line number has a limit, must keeps between from 2 to 80 lines. The values set up by the alternated register become enable when NLIN control bit is "1". When NLIN control bit is "0", alternated drive waveform reverses by each frame is generated.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
N7 0 0
N6 0 0
N5 0 0
N4 0 0
1
0
0
0
N3 0 0 0
N2 0 0
N1 0 0
N0 0 1
Line Address 2
0
0
0
129
Alternated Timing (i) NLIN="0" (in case of 1/130 DUTY Display)
1st Line
2nd Line
3rd Line
129st Line
130th Line 1st Line
LP
FLM
M
(ii)
NLIN="1"
nth line Cycle
1st Line
2nd Line
3rd Line
nth Line
1st Line
2nd Line
LP
M
8.2.5 Display Control (1) Register D7 1 D6 0 D5 0 D4 0 D1 D0 ALL ON/ SHIFT MON ON OFF D3 D2 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {SHIFT, MON, ALLON, ON/OFF}=0H, read address: 8H) Various control of display is set up. ON/OFF To control ON/OFF of display ON/OFF = "0": Display OFF * This specification is subject to be changed without notice. 69 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
ON/OFF = "1": Display ON ALLON Regardless of the data for display, all is on. This control has priority over display normal/reverse commands. ALLON = "0": Normal display ALLON = "1": All display lighted MON Select Monochrome or Gradation display MON = "0": Gradation display mode MON = "1": Monochrome display mode SHIFT The shift direction of display scanning data in the common driver output is selected. SHIFT = "0": COM0 COM127 shift-scan SHIFT = "1": COM127 COM0 shift-scan 8.2.6 Display Control (2) Register D7 1 D6 0 D5 0 D4 D3 D2 D1 D0 1 REV NLIN SWAP REF CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {REV,NLIN,SWAP,REF}=0H, read address: 9H) Various control of display is set up.
REF When MPU accesses to display RAM, the X address and data can reverse. The REF function shows in the table below: Access from MPU X Address D7-D0 D0(LSB) NH D7(MSB) D0(LSB) NH D7(MSB) Internal Access X Address D7-D0 (LSB) NH (MSB) (MSB) MaxH-NH (LSB) Corresponding Segment Output SEG(8*NH)Output SEG(8*NH+7)Output SEG(8*(maxH-NH)+7)Output SEG(8*(maxH-NH))Output
REF 0
1
Note: maxH: The maximum X-address in each access mode. The order of segment driver output can be reversed by register by register setting, lessening the limitation in placing IC when assembling a LCD module.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
SWAP When data to display RAM are written, the write data exchange bit order. SWAP = "0": Normal mode. SWAP = "1": in data writing, exchange bit order. Example of exchange bit order
Write Data
SWAP=0
SWAP=1
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Internal Data
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d11d10 d9 d8 d7 d6 d5 d4 d3 d2
d1
d0
8 bit access (HSW=1)
Write Data SWAP=0 SWAP=1
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Internal Data
d0 d1 d2 d3 d4 d5 d6 d7
d7 d6 d5 d4 d3 d2 d1 d0
16 bit access (HSW=1)
Write Data
SWAP=0
SWAP=1
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12D13D14 D15
Internal Data
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d15 d14 d13d12d11d10 d9 d8 d7 d6 d5 d4 d3 d2
d1
d0
CAUTION: REF and SWAP both set to "1" When data write to display RAM, the write data is normal bit order. When data read from display RAM, the read data is exchanged bit order. NLIN The NLIN control n-line alternated drive. NLIN = "0": n-line alternated drive OFF. In each frame, the alternated signals (M) are reversed. NLIN ="1": n-line alternated drive ON. According to data set up in n-line alternated register, the alternation is made. * This specification is subject to be changed without notice. 71 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
REV Corresponding to the data of display RAM, the lighting or not-lighting of the display is set up. REV ="0": When RAM data at "H", LCD at ON voltage (normal) REV ="1": When RAM data at "L", LCD at ON voltage (reverse) 8.2.7 Increment Control Register Set D7 1 D6 0 D5 1 D4 D3 D2 D1 D0 0 WIN AIM AYI AXI CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the tine of reset: {WIN,AIM,AYI,AXI}=0H, read address: AH) This register control the increment mode and window function when accessing to display RAM. The increment operation of AX and AY register can control by AIM,AYI and AXI registers setting and every write access or every read access to display RAM. The AY register directly connect to display RAM as Y address. The AX register connect to address converter, and that output to display RAM as X address in the auto increment mode, AX and AY register are increment, not directly increment X and Y address. In setting to this control register, the increment operation of address can be made without setting successive addresses for writing data or for reading data to display RAM from MPU. The WIN register use for window function control. WIN="0": Normal RAM access WIN="1": Window function access In case of using window function access, should be set following register before access to RAM. WIN="1", AXI="1", AYI="1" X Address, Y Address, Window X End Address, Window Y End Address Moreover, should be keep following address condition. Window end X address Window start X address Window end Y address Window start Y address Detail of window function see "6-7 Display RAM access using Window Function". The increment control of X and Y addresses by AIM, AYI and AXI registers are as follows. AIM 0 1 Address Increment Timing When writing to Display RAM or reading from Display RAM This is effective when access to successive address area Only when writing to Display RAM This is effective the case of "Read Modify Write AXI 0 1 0 1 Select Address Increment Operation Address is not increment X-Address is increment Y-Address is increment X and Y both are increment Remark (1) (2) (3) (4)
AYI 0 0 1 1
(1) Regardless of AIM, no increment for AX and AY register. * This specification is subject to be changed without notice. 72 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(2) According to the setting-up of AIM, automatically change X address. In accordance with the REF register, AX register and X address becomes as follows.
REF 0 1
Transition of AX Register 00H 01H ....... max
Transition of X Address Same as AX register max maxH ..... 00H
Note: maxH: The internal maximum X-address in each access mode. (3) According to the setting-up of AIM, automatically change Y address. Regardless of REF, increment by loop of
Transition of AY Register
Transition of Y Address Same as AY register
00H
01H
.......
51H
(4) According to the setting-up of AIM, cooperative change X and Y address. When the X address exceed maxH, Y address increment occurs.
REF 0 1
Transition of AX and AY Register
AX: 00H 00H max AY: When each AX exceed maxH, increment AY 00H 00H 51H
Transition of X and Y Address Same as AX and AY register
AX: max AY: maxH 00H
Same as AY register
Note: maxH: The internal maximum X-address in each access mode. Following shows address increment in window function access.
REF 0 1
Transition of AX and AY Register
AX:
START Address START Address+1 END Address
Transition of X and Y Address Same as AX and AY register
AX:
maxH(START Address) maxH(START Address+1) maxH(END Address)
AY: When each AX exceed AE, increment AY
START Address START Address+1 END Address
AY: Same as AY register
Note: maxH: The internal maximum X-address in each access mode.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
In each operation mode, the following increment operation is performed: (i) (ii) When gradation display mode and 8-bit access are selected Address are incremented as described above. When gradation display mode and 16-bit access are selected: Two bytes are accessed by accessing the RAM once. The X-addresses increment in the order of 00H,01H,...3EH,and 3FH. 8.2.8 Power Control Register D7 1 D6 0 D5 1 D4 D3 D2 D1 D0 1 AMPON HALT DCON ACL CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the tine of reset: {AMPON, HALT,DCON,ACL}=0H, read address: BH)
ACL The internal circuit can be initialized. This register is effective only at Master operation mode. ACL = "0": Normal operation ACL = "1": Initialization ON When the reset operation begins internally after ACL register sets to "1", the ACL register is automatically cleared to "0". The internal reset signal has been generated with a clock (built-in oscillation circuit or CK input) for the display. Therefore, install the WAIT period for the display clock two cycles at least. After WAIT period, next operation can handle. Since built-in oscillation circuit and external CK input can not be used in the slave mode, the setting of the ACL register becomes the invalidity. Certainly use the RESB terminal, when the reset is applied on the slave chip.
DCON The internal booster circuit is set ON/OFF DCON = "0": Booster circuit OFF DCON="1": Booster circuit ON
HALT The conditions of power saving are set ON/OFF by this command. HALT = "0": Normal operation HALT="1": Power-saving operation When setting in the power-saving state, the consumed current can be reduced to a value near to the standby current. The internal condition at power saving are as follows. (a) (b) (c) The oscillating circuit and power supply circuit are stopped. The LCD drive is stopped, and output of the segment driver and common driver are VSS level. The clock input from CK pin is inhibited. 74 2005/3/8 (V1.2)
* This specification is subject to be changed without notice.
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(d) (e)
The contents of Display RAM data are maintained. The operational mode maintains the state of command execution before executing power saving command.
AMPON Command The internal OP-AMP circuit block (voltage regulator, electronic volume, and voltage conversion circuit) is set ON/OFF by this command. AMPON = "0": The internal OP-AMP circuit OFF AMPON = "1": The internal OP-AMP circuit ON 8.2.9 LCD Duty (DS) D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 DS3 DS2 DS1 DS0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {DS3, DS2, DS1, DS0}=0H, read address: CH) Mark shows "Don't care"
The DS register set to LCD display duty. DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Display width and Duty 8-dot width display in Y-direction, 1/10 duty 16-dot width display in Y-direction, 1/18 duty 24-dot width display in Y-direction, 1/26 duty 32-dot width display in Y-direction, 1/34 duty 40-dot width display in Y-direction, 1/42 duty 48-dot width display in Y-direction, 1/50 duty 56-dot width display in Y-direction, 1/58 duty 64-dot width display in Y-direction, 1/66 duty 72-dot width display in Y-direction, 1/74 duty 80-dot width display in Y-direction, 1/82 duty 88-dot width display in Y-direction, 1/90 duty 96-dot width display in Y-direction, 1/98 duty 104-dot width display in Y-direction, 1/106 duty 112-dot width display in Y-direction, 1/114 duty 120-dot width display in Y-direction, 1/122duty 128-dot width display in Y-direction, 1/130 duty
Partial display can be made possible by setting an arbitrary duty ratio. 8.2.10 Booster Setup (VU) D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 VU2 VU1 VU0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {VU2,VU1,VU0}=0H, read address: DH) Mark shows "Don't care"
The booster steps set to VU register * This specification is subject to be changed without notice. 75 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
. VU2 0 0 0 0 1 1 1 1 VU1 0 0 1 1 0 0 1 1 VU0 0 1 0 1 0 1 0 1 Booster Operation Booster disable (No operation) 2 times voltage output 3 times voltage output 4 times voltage output 5 times voltage output 6 times voltage output Prohibit code Prohibit code
8.2.11 Bias Setting Register (B) D7 1 D6 1 D5 1 D4 0 D3 D2 B2 D1 B1 D0 B0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {B2,B1,B0}=0H, read address: EH) Mark shows "Don't care"
This register is used to set a bias ratio. A bias ratio can be selected from 1/5 to 1/12 by setting B2, B1, and B0. B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Bias 1/5 Bias 1/6 Bias 1/7 Bias 1/8 Bias 1/9 Bias 1/10 Bias 1/11 Bias 1/12 Bias
8.2.12 Register Access Control D7 1 D6 1 D5 1 D4 D3 D2 D1 D0 0 TST0 RE2 RE1 RE0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0/1 0/1 0/1
(At the time of reset: {TST0,RE2,RE1,RE0}=0H, read address: FH) Mark shows "Don't care"
The RE register set to number of register bank. Access to each control register, set RE register at first. The TST0 register use for test of LSI, Therefore this register must be set to "0" 8-13 Gradation Palette Register (PA0~PA7, PB0~PB7, PC0~PC7) D7 0 D6 0 D5 0 D4 D3 D2 D1 D0 0 PA03 PA02 PA01 PA00 /PA83 /PA82 /PA81 /PA80 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 0H) * This specification is subject to be changed without notice. 76 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
D7 0
D6 0
D5 0
D4 1
D3
D2
D1 D0 PA04 /PA84
CSB 0
RS 1
RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 1H) (At the time of reset: PA04~PA00 = "00000") D7 0 Mark shows "Don't care" D6 0 D5 1 D4 D3 D2 D1 D0 0 PA13 PA12 PA11 PA10 /PA93 /PA92 /PA91 /PA90 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 2H) D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 PA14 /PA94 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 3H) (At the time of reset: PA14~PA10 = "00101") D7 0 Mark shows "Don't care" D6 1 D5 0 D4 0 D3 D2 D1 D0 PA23 PA22 PA21 PA20 /PA103 /PA102 /PA101 /PA100 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 4H) D7 0 D6 1 D5 0 D4 1 D3 D2 D1 D0 PA24 /PA104 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 5H) (At the time of reset: PA24~PA20 = "01010") D7 0 Mark shows "Don't care" D6 1 D5 1 D4 0 D3 D2 D1 D0 PA33 PA32 PA31 PA30 /PA113 /PA112 /PA111 /PA110 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 6H) D7 0 D6 1 D5 1 D4 1 D3 D2 D1 D0 PA34 /PA114 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 7H) (At the time of reset: PA34~PA30 = "01110") Mark shows "Don't care"
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
D7 1
D6 0
D5 0
D4 0
D3 D2 D1 D0 PA43 PA42 PA41 PA40 /PA123 /PA122 /PA121 /PA120
CSB 0
RS 1
RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 8H) D7 1 D6 0 D5 0 D4 1 D3 D2 D1 D0 PA44 /PA124 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: 9H) (At the time of reset: PA44~PA40 = "10001") D7 1 Mark shows "Don't care" D6 0 D5 1 D4 0 D3 D2 D1 D0 PA53 PA52 PA51 PA50 /PA133 /PA132 /PA131 /PA130 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: AH) D7 1 D6 0 D5 1 D4 1 D3 D2 D1 D0 PA54 /PA134 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: BH) (At the time of reset: PA54~PA50 = "10101") D7 1 Mark shows "Don't care" D6 1 D5 0 D4 0 D3 D2 D1 D0 PA63 PA62 PA61 PA60 /PA143 /PA142 /PA141 /PA140 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: CH) D7 1 D6 1 D5 0 D4 1 D3 D2 D1 D0 PA64 /PA144 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 1
(Read address: DH) (At the time of reset: PA64~PA60 = "11010") D7 0 Mark shows "Don't care" D6 0 D5 0 D4 0 D3 D2 D1 D0 PA73 PA72 PA71 PA70 /PA153 /PA152 /PA151 /PA150 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 0H) D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 PA74 /PA154 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 1H) * This specification is subject to be changed without notice. 78 2005/3/8 (V1.2)
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(At the time of reset: PA74~PA70 = "11111") D7 0 Mark shows "Don't care" D6 0 D5 1 D4 D3 D2 D1 D0 0 PB03 PB02 PB01 PB00 /PB83 /PB82 /PB81 /PB80 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 2H) D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 PB04 /PB84 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 3H) (At the time of reset: PB04~PB00 = "00000") D7 0 Mark shows "Don't care" D6 1 D5 0 D4 D3 D2 D1 D0 0 PB13 PB12 PB11 PB10 /PB93 /PB92 /PB91 /PB90 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 4H) D7 0 D6 1 D5 0 D4 1 D3 D2 D1 D0 PB14 /PB94 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 5H) (At the time of reset: PB14~PB10 = "00101") D7 0 Mark shows "Don't care" D6 1 D5 1 D4 0 D3 D2 D1 D0 PB23 PB22 PB21 PB20 /PB103 /PB102 /PB101 /PB100 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 6H) D7 0 D6 1 D5 1 D4 1 D3 D2 D1 D0 PB24 /PB104 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 7H) (At the time of reset: PB24~PB20 = "01010") D7 1 Mark shows "Don't care" D6 0 D5 0 D4 0 D3 D2 D1 D0 PB33 PB32 PB31 PB30 /PB113 /PB112 /PB111 /PB110 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 8H)
* This specification is subject to be changed without notice.
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D7 1
D6 0
D5 0
D4 1
D3
D2
D1
D0 PB34 /PB114
CSB 0
RS 1
RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: 9H) (At the time of reset: PB34~PB30 = "01110") D7 1 Mark shows "Don't care" D6 0 D5 1 D4 0 D3 D2 D1 D0 PB43 PB42 PB41 PB40 /PB123 /PB122 /PB121 /PB120 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: AH) D7 1 D6 0 D5 1 D4 1 D3 D2 D1 D0 PB44 /PB124 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: BH) (At the time of reset: PB44~PB40 = "10001") D7 1 Mark shows "Don't care" D6 1 D5 0 D4 0 D3 D2 D1 D0 PB53 PB52 PB51 PB50 /PB133 /PB132 /PB131 /PB130 D3 D2 D1 D0 PB54 /PB134 CSB 0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: CH) D7 1 D6 1 D5 0 D4 1 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 0
(Read address: DH) (At the time of reset: PB54~PB50 = "00101") D7 0 Mark shows "Don't care" D6 0 D5 0 D4 0 D3 D2 D1 D0 PB63 PB62 PB61 PB60 /PB143 /PB142 /PB141 /PB140 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 0H) D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 PB64 /PB144 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 1H) (At the time of reset: PB64~PB60 = "11010") Mark shows "Don't care"
* This specification is subject to be changed without notice.
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D7 0
D6 0
D5 1
D4 0
D3 D2 D1 D0 PB73 PB72 PB71 PB70 /PB153 /PB152 /PB151 /PB150 D3 D2 D1 D0 PB74 /PB154 CSB 0
CSB 0
RS 1
RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 2H) D7 0 D6 1 D5 0 D4 1 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 3H) (At the time of reset: PB74~PB70 = "11111") D7 0 Mark shows "Don't care" D6 1 D5 0 D4 D3 D2 D1 D0 0 PC03 PC02 PC01 PC00 /PC83 /PC82 /PC81 /PC80 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 4H) D7 0 D6 1 D5 0 D4 1 D3 D2 D1 D0 PC04 /PC84 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 5H) (At the time of reset: PC04~PC00 = "00000") D7 0 Mark shows "Don't care" D6 1 D5 1 D4 D3 D2 D1 D0 0 PC13 PC12 PC11 PC10 /PC93 /PC92 /PC91 /PC90 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 6H) D7 0 D6 1 D5 1 D4 1 D3 D2 D1 D0 PC14 /PC94 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 7H) (At the time of reset: PC14~PC10 = "00101") D7 1 Mark shows "Don't care" D6 0 D5 0 D4 0 D3 D2 D1 D0 PC23 PC22 PC21 PC20 /PC103 /PC102 /PC101 /PC100 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 8H) D7 1 D6 0 D5 0 D4 1 D3 D2 D1 D0 PC24 /PC104 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: 9H) (At the time of reset: PC24~PC20 = "01010") * This specification is subject to be changed without notice. 81 2005/3/8 (V1.2)
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D7 1
Mark shows "Don't care" D6 0 D5 1 D4 0 D3 D2 D1 D0 PC33 PC32 PC31 PC30 /PC113 /PC112 /PC111 /PC110 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: AH) D7 1 D6 0 D5 1 D4 1 D3 D2 D1 D0 PC34 /PC114 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: BH) (At the time of reset: PC34~PC30 = "01110") D7 1 Mark shows "Don't care" D6 1 D5 0 D4 0 D3 D2 D1 D0 PC43 PC42 PC41 PC40 /PC123 /PC122 /PC121 /PC120 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: CH) D7 1 D6 1 D5 0 D4 1 D3 D2 D1 D0 PC44 /PC124 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
(Read address: DH) (At the time of reset: PC44~PC40 = "10001") D7 0 Mark shows "Don't care" D6 0 D5 0 D4 0 D3 D2 D1 D0 PC53 PC52 PC51 PC50 /PC133 /PC132 /PC131 /PC130 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(Read address: 0H) D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 PC54 /PC134 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(Read address: 1H) (At the time of reset: PC54~PC50 = "10101") D7 0 Mark shows "Don't care" D6 0 D5 1 D4 0 D3 D2 D1 D0 PC63 PC62 PC61 PC60 /PC143 /PC142 /PC141 /PC140 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(Read address: 2H)
* This specification is subject to be changed without notice.
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D7 0
D6 0
D5 1
D4 1
D3
D2
D1
D0 PC64 /PC144
CSB 0
RS 1
RDB WRB RE2 RE1 RE0 1 0 1 0 0
(Read address: 3H) (At the time of reset: PC64~PC60 = "11010") D7 0 Mark shows "Don't care" D6 1 D5 0 D4 0 D3 D2 D1 D0 PC73 PC72 PC71 PC70 /PC153 /PC152 /PC151 /PC150 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(Read address: 4H) D7 0 D6 1 D5 0 D4 1 D3 D2 D1 D0 PC74 /PC154 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(Read address: 5H) (At the time of reset: PC74~PC70 = "11111") Mark shows "Don't care"
These gradation palette register set up gradation level. The EM65568 has 32 gradation levels. Gradation level table 4096 color mode [Three groups of palettes Aj,Bj, and Cj (j=0-15) are available]
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Gradation level 0 1/31 2/31 3/31 4/31 5/31 6/31 7//31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Remarks gradation palette0 initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Palette 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Remarks gradation palette8 initial value gradation palette9 initial value gradation palette10 initial value gradation palette11 initial value gradation palette12 initial value gradation palette13 initial value gradation palette14 initial value gradation palette15 initial value
gradation palette1 initial value gradation palette2 initial value gradation palette3 initial value gradation palette4 initial value gradation palette5 initial value gradation palette6 initial value gradation palette7 initial value
* This specification is subject to be changed without notice.
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256 color mode [Three groups of palettes Aj,Bj, and Cj (j=0-7) are available]
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Gradation level 0 1/31 2/31 3/31 4/31 5/31 6/31 7//31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Remarks 256 color palette0 initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Palette 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Remarks 256 color palette4 initial value
256 color palette1 initial value
256 color palette5 initial value
256 color palette2 initial value
256 color palette6 initial value
256 color palette3 initial value
256 color palette7 initial value
8.2.14 Display Start Common D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 SC3 SC2 SC1 SC0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(At the time of reset:{ SC2,SC1,SC0}=0H, read address: 6H) Mark shows "Don't care"
The SC register set up the scanning start output of the common driver. SC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Display starting common when Display starting common when SHIFT=0 SHIFT=1 COM0~ COM127~ COM8~ COM119~ COM16~ COM111~ COM24~ COM103~ COM32~ COM95~ COM40~ COM87~ COM48~ COM79~ COM56~ COM71~ COM64~ COM63~ COM72~ COM55~ COM80~ COM47~ COM88~ COM39~ COM96~ COM31~ COM104~ COM23~ COM112~ COM15~ COM120~ COM7~ Prohibit code Prohibit code
SHIFT="0": COM0 to COM127 shift-scan SHIFT="1": COM127 down to COM0 shift-scan * This specification is subject to be changed without notice. 84 2005/3/8 (V1.2)
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8.2.15 Display Select Control D7 1 PS In 4096 color mode, select 16 gradation level from 32 gradation palette. In 256 color mode, just setting lower 8 gradation. PS= "0":Lower 8 gradation setting PS= "1":Upper 8 gradation setting D6 0 D5 0 D4 D3 D2 D1 0 PWM GLSB D0 PS CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(At the time of reset: {PWM,GLSB, PS} = 0H, read address: 8H)
GLSB In 256 color mode, for the segment driver of 4-gradation display, select 4 gradations from 8 gradations using the 2 bits written to the corresponding RAM area and the 1 bit supplemented by the gradation LSB circuit. Supplement the 1 bit of data by setting the gradation LSB register (GLSB). Gradation LSB = "0": Selects 0 as the LSB information on the RAM for 4-gradation segment driver. Gradation LSB = "1": Selects 1 as the LSB information on the RAM for 4-gradation segment driver.
PWM The PWM register select the gradation display mode. PWM = "0": Variable display mode using 16 gradations selected from 32 gradations in 4096 color mode Variable display mode using 8 gradations selected from 32 gradations in 256 color mode (C256=1) PWM = "1": 16-gradation fixed display mode 8.2.16 Data Bus Size Select D7 1 D6 0 D5 0 D4 D3 D2 D1 D0 1 C256 HSW ABS WLS CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(At the time of reset: {C256,HSW,ABS,WLS} = 0H, read address: 9H) Mark shows "Don't care"
The WLS register select data bus size for access from MPU WLS = "0": The data bus size is 8-bits width WLS = "1": The data bus size is 16-bits width When MPU access to control register using 16-bits bus size , high byte data is ignored.
ABS ABS= "0": normal mode ABS= "1": change corresponding bit from input data bus
* This specification is subject to be changed without notice.
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HSW HSW="0": High speed writing mode off HSW="1": High speed writing mode on accessing the 8-bit data RAM
C256 C256= "0": 4096 color mode C256= "1": 256 color mode 8.2.17 Electronic Volume Register D7 1 D6 0 D5 1 D4 D3 D2 D1 D0 0 DV3 DV2 DV1 DV0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(Read address: AH) D7 1 D6 0 D5 1 D4 1 D3 D2 D1 D0 DV6 DV5 DV4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(Read address: BH) (At the time of reset: {DV6~DV0} = 00H) Mark shows "Don't care" The DV register can control V0 voltage. The DV register has 7-bits, so can select 128 level voltage. DV6 0 0 DV5 0 0 DV4 0 0 DV3 0 0 1 1 DV2 0 0 DV1 0 0 DV0 0 1 Output voltage Smaller Larger
1 1
1 1
1 1
1 1
1 1
0 1
The output voltage at VREG is specified by equation (1). VREG = VREF * N -----------------------------------------------------------(1) (N: Number of boosting steps) The LCD drive voltage V0 is determined by VREG level and electronic volume code equation (2). V0 = 0.5 * VREG + M * (VREG - 0.5VREG) / 127 --------------------------(2) (M: DV6 to DV0 register values)
In order to prevent transient voltage from generating when an electronic volume code is set, the circuit design is such that the set value is not reflected as a level immediately after only the upper bits(DV6-DV4) of the electronic code have been set. The set value becomes valid when the lower bits (DV3-DV0) of the electronic control volume code have also been set.
* This specification is subject to be changed without notice.
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8.2.18 Resistance Ratio of CR Oscillator D7 1 D6 1 D5 0 D4 1 D3 D2 D1 D0 RF2 RF1 RF0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(At the time of reset: {RF2, RF1, RF0} = 0H, read address: DH) Mark shows "Don't care"
The RF registers can control resistance ratio of CR oscillator. Therefore frame frequency can change RF registers setting. When change RF registers value, should be need to check LCD display quality. RF2 RF1 RF0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Operation Initial Resistance Ratio 0.7 times of initial Resistance Ratio 0.85 times of initial Resistance Ratio 1.15 times of initial Resistance Ratio 1.3 times of initial Resistance Ratio Prohibit Code Prohibit Code Prohibit Code
* This specification is subject to be changed without notice.
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8.2.19 Extended power control D7 1 D6 1 D5 1 D4 0 D3 D2 D1 D0 BF1 BF0 HPM DIS CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(At the time of reset: {HPM, DIS} = 0H, {BF1,BF0}=0H;read address: EH) The DIS register can control capacitors discharged that connected between the power supply V0-V4 for LCD drive voltage and VSS. When using this register, refer to 6-30 (Discharge circuit). DIS = "0": Discharge OFF DIS = "1": Discharge start The HPM register is the power control for the power supply circuit for liquid crystal drive. HPM= "H": High power mode HPM= "L": Normal mode BF1~BF0: The operating frequency in the booster is selected. When the boosting frequency is high, the driving ability of booster become high, but the current consumption is increased. Adjust the boosting frequency considering the external capacitors and the current consumption. BF1 0 0 1 1 BF0 0 1 0 1 Operating clock frequency in the booster 1.5K Hz * 8 1.5K Hz * 4 1.5K Hz * 2 1.5 K Hz
8.2.20 Internal Register Read Address D7 1 D6 1 D5 0 D4 1 D3 D2 D1 D0 RA3 RA2 RA1 RA0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
(At the time of reset: {RA3,RA2,RA1,RA0} = BH) The RA register set to specify the address for register read operation. The EM65568 has many registers and has register bank. Therefore, it is need 4-steps to read to read the specific register in maximum case. (1) (2) (3) (4) Write 04H to RE register for access to RA register. Writes specific register address to RA register. Write specific register bank to RE register. Read specific contents.
* This specification is subject to be changed without notice.
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8.2.21 Internal Register Data Read D7 D6 D5 D4 D3 D2 D1 D0 Internal Register read data CSB 0 RS 1 RDB WRB RE2 RE1 RE0 0 1 0/1 0/1 0/1
Mark shows "Don't care"
This command is used to read data from an internal register. Before executing the command, you need to set the address and RE flag for reading data from the internal register. 8.2.22 Windows End X Address D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 EX3 EX2 EX1 EX0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
(At the time of reset: {EX3,EX2,EX1,EX0} = 0H, read address: 0H) D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 EX7 EX6 EX5 EX4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
(At the time of reset: {EX7, EX6,EX5,EX4} = 0H, read address: 1H) Mark shows "Don't care"
The EX registers set to X direction end address for window function. 8.2.23 Windows End Y Address D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 EY3 EY2 EY1 EY0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
(At the time of reset: {EY3, EY2, EY1, EY0} = 0H, read address: 2H) D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 EY7 EY6 EY5 EY4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
(At the time of reset: {EY7, EY6, EY5, EY4} = 0H, read address: 3H) Mark shows "Don't care" The EY registers set to Y direction end address for window function.
* This specification is subject to be changed without notice.
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8.2.24 Line Reverse Start Address D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 LS3 LS2 LS1 LS0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
(At the time of reset: {LS3,LS2,LS1,LS0} = 0H, read address: 4H) D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 LS6 LS5 LS4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
(At the time of reset: {LS6, LS5, LS4} = 0H, read address: 5H) Mark shows "Don't care"
The LS registers set to line reverse start address. Moreover, must keep following two conditions. (1) 00H LS 7FH (2) LS LE LE: Line reverse end address
8.2.25 Line Reverse End Address D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 LE3 LE2 LE1 LE0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
(At the time of reset: {LE3, LE2, LE1, LE0} = 0H, read address: 6H) D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 LE6 LE5 LE4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
(At the time of reset: { LE6, LE5, LE4} = 0H, read address: 7H) Mark shows "Don't care"
The LE registers set to line reverse end address. Moreover, must keep following two conditions. (3) 00H LS 7FH (4) LS LE LS: Line reverse start address
8.2.26 Line Reverse Control D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 BT LREV CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
(At the time of reset: {BT,LREV} = 0H, read address: 8H) Mark shows "Don't care"
The LREV registers control line reverse display function. LREV = "0": Normal display (Not reverse). LREV = "1": Line reverse display enable. The area specified by Line Reverse Start/End Register reverse display. * This specification is subject to be changed without notice. 90 2005/3/8 (V1.2)
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The reverse type is selectable by BT register. When use Line Reverse Display function, LS and LE registers must keep following relation. LS LE
The BT register control line reverse type. This is an option of line reverse display function. This BTs setting is only available in case of LREV="1" BT = "0": Reverse display BT = "1": Reverse display at each 32 frame.
Display change each 32 frame
Blink example(LREV="1", BT="1")
The special segment outputs aren't influenced by LREV and BT setting. The display area by selected COMA and COMB common outputs aren't also influenced.
ELAN LCD DRIVER Low Power and Low Voltage
Display change each 32 frame
ELAN
Line reverse start address
LCD DRIVER Low Power and Low Voltage
Line reverse end address
Blink example (LREV="1", BT="1")
* This specification is subject to be changed without notice.
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9.
Relationship between Setting and Common/Display RAM
The relationship between the COM pin numbers and the addresses in the Y-direction on the display RAM changes according to the SHIFT command. LCD Duty Set command. Display Starting Common Position Set command, and Display Starting Line Set command. When "0" is selected for the display starting line: The relationship between the COM pin and the addresses in the vertical direction of the display RAM (hereafter called MY) changes on an 15 dots basis according to the LCD Duty Set command and the Display Starting Common Position Set command. When the SHIFT bit is "0", the common position change in the forward direction. When "1" they change reverse direction. When "0" is selected as the values for LA7 to LA0 in the Display Starting Line Set command, the MY number corresponding to the display starting position is "0". The MY numbers are sequentially shifted backward when display occurs. In any case, the relations of COMA = MY128 and COMB = MY129 do not change. When non-zero is selected for the display starting line: The relationship between the COM pins and the addresses in the vertical direction on the display RAM, MY changes on an 15 dots basis according to the information in the LCD Duty Set command and Display Starting Common Position Set command. The common positions change in the forward when the SHIFT bit is "0", and change in the reverse direction when the SHIFT bit is "1". If non-zero is selected for the values for LA7 to LA0 by the Display Starting Line set command. the MY number corresponding to the display starting position shifts by the set value. The MY number shifts backward when display occurs. If it exceeds 128, it returns to 0, and the shifts sequentially. In any case, the relations of COMA = MY129 and COMB = MY129 do not change.
* This specification is subject to be changed without notice.
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10. Absolute maximum ratings
10.1 Absolute maximum ratings Item Supply voltage (1) Supply voltage (2) Supply voltage (3) Supply voltage (4) Supply voltage (5) Supply voltage (6) Input voltage Storage temperature Symbol VDD VEE VOUT VREG V0 V1,V2,V3,V4 VI Tstg Condition Pin use VDD VEE VOUT VREG V0 V1,V2,V3,V4 *1 Rating -0.3 ~ + 4.0 -0.3 ~ + 4.0 --0.3 ~ + 16.0 -0.3 ~ + 16.0 -0.3 ~ + 16.0 -0.3 ~ V0+ 0.3 -0.3 ~ VDD+ 0.3 -45 ~ +125 Unit V V V V V V V
Ta=25
10.2 Recommended operating conditions Item Supply voltage Operating voltage Symbol VDD1 VDD2 VEE V0 VOUT VREG VREF Topr Pin VDD VEE V0 VOUT VREG VREF Min. 2.2 2.4 2.4 5 2.1 -30 Typ. Max. Unit Note 3.3 V *1 3.3 V *2 3.3 V *3 15 V *4 15 V VOUT*0.9 V 3.3 V *5 85
Operating temperature
*1 In case of VBA output doesn't use. *2 In case of VBA output use. *3 Power supply for internal boosting circuit. If applied voltage same as VDD, connect to VDD. *4 Voltage V0>V1>V2>V3>V4>VSS must always satisfied. *5 Voltage VEE > VREF must always satisfied.
* This specification is subject to be changed without notice.
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EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
11. DC characteristics
VSS=0V , VDD = 2.2 ~3.3V , Ta = -30 ~85 Item High level input voltage Low level input voltage High level output current Low level output current High level output current Low level output current Input leakage current Output leakage current LCD driver output resistance Standby current through VDD pin Oscillator frequency (variable gradation mode, 4096 or 256 color mode) Oscillator frequency (16 gradation mode) Oscillator frequency (8 gradation mode) Oscillator frequency (monochrome mode) Booster output voltage on VOUT pin Symbol VIH VIL IOH1 IOL1 IOH2 IOL2 ILI1 ILI2 ILO RON ISTB Fosc1 Fosc2 Fosc3 Fosc4 VOUT1 VOUT1 VOUT2 VOUT3 VOUT4 IDD1 IDD2 Current consumption IDD3 IDD4 IDD5 VBA output voltage VREG output voltage VBA VREG VOH = VDD-0.4V VOL= 0.4V VOH = VDD-0.4V VOL= 0.4V VI = VSS or VDD VI = VSS or VEE VI = VSS or VDD V0=10V V0=6V CK=0, CSB=VDD, Ta=25 , VDD=3V |Von| = 0.5V VDD=3V , Ta=25, Rf setting = (Rf2,Rf1,Rf0)=(000) VDD=3V, Ta=25 , Rf setting = (Rf2,Rf1,Rf0)=(000) VDD=3V, Ta=25 , Rf setting = (Rf2,Rf1,Rf0)=(000) VDD=3V , Ta=25, Rf setting = (Rf2,Rf1,Rf0)=(000) Six times boosting RL = 500K (VOUT-VSS) Five times boosting RL = 500K (VOUT-VSS) Four times boosting RL = 500K (VOUT-VSS) Three times boosting RL = 500K (VOUT-VSS) Two times boosting RL = 500K(VOUT-VSS) VDD = 3V, 6 times booster, All ON pattern (color), display on VDD = 3V, 6 times booster, Checker pattern (color) VDD = 3V, 5 times booster, All ON pattern (color), display on VDD = 3V, 5 times booster, Checker pattern (color) VDD = 3V, 6 times booster, ALL ON pattern (mono), display off VDD =2.4V~3.3V VEE =2.4~3.3V,VREF=0.9VEE, N times boosting (N=2 to 6) 94 Condition Min. 0.8VDD 0 -2.4 2.4 -0.8 0.8 -2 -0.3 -2 1.0 1.2 Typ. 0.9VDD 0.1VDD -3.2 3.2 -1.0 1.0 0 0 0 1.3 1.7 5 450 255 115 18 6*VEE *0.95 5*VEE *0.95 4*VEE *0.95 3*VEE *0.95 2*VEE *0.95 320 370 220 260 150 200 420 480 290 340 300 530 300 135 21 Max. VDD 0.2VDD -4.5 4.5 -1.2 1.2 2 0.3 2 1.6 2.2 15 610 345 155 24 Unit V V mA mA mA mA A A A K A KHz KHz KHz KHz V V V V V A A A A uA V V Pin used 1 1 2 2 3 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 VBA 23
0.9VDD*0.97 0.9VDD 0.9VDD*1.03 (VREF*N) VREF*N (VREF*N) *0.95 *1 *1.03
* This specification is subject to be changed without notice.
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Relationship of oscillating frequency (fosc) and external clock frequency (fCK) to LCD frame frequency (fFLM) is each display mode Original oscillating clock When use built-in oscillating circuit (fosc) Display mode Variable gradation Simple gradation (4096 color) Simple gradation (256 color) Monochrome Variable gradation Simple gradation (4096 color) Simple gradation (256 color) Monochrome Ratio of display duty cycle (1/D) Pin used 1/130 to 1/82 1/74 to 1/42 1/34 to 1/26 1/18 to 1/10 fosc /(2*31*D) fosc /(4*31*D) fosc /(8*31*D) fosc /(16*31*D) fosc/(2*15*D) fosc/(4*15*D) fosc/(8*15*D) fosc/(16*15*D) fosc /(2*7*D) fosc /(4*7*D) fosc /(8*7*D) fosc /(16*7*D) FLM
When use external clock from CK pin. (fCK)
fosc /(2*1*D) fosc /(4*1*D) fosc /(8*1*D) fosc /(16*1*D) fCK/(2*31*D) fCK /(4*31*D) fCK /(8*31*D) fCK /(16*31*D) fCK /(2*15*D) fCK /(4*15*D) fCK /(8*15*D) fCK /(16*15*D) fCK /(2*7*D) fCK /(2*1*D) fCK /(4*7*D) fCK /(4*1*D) fCK /(8*7*D) fCK /(8*1*D) fCK /(16*7*D) fCK /(16*1*D)
Pin used: 1 D0-D15, CSB, RS, M/S, M86, RDB, WRB, CK, CKS, CLK, LP, FLM, M, P/S, RESB, TEST pins. 2 D0~D15 pins 3 LP, FLM, M, CLK pins 4 CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins 5 VREF pin 6 Applied when D0~D15, CLK, LP, FLM, and M are in the state of high impedance. 7 SEGA0~SEGA127, SEGB0~SEGB127, SEGC0~SEGC127. DSEGA0~DSEGA1, DSEGB0~DSEGB0 , DSEGC0~DSEGC1 , COM0~COM79, COMA, COMB pins Resistance when being applied 0.5V between each output pin and each power supply (V0, V1, V2, V3, V4) and when being applied 1/9 bias. 8 VDD pin, VDD pin current without load at the stoppage of original oscillating clock and at non-select (CSB=VDD) 9 Oscillating frequency, when using the built-in oscillating circuit (variable gradation display mode,4096 or 256 color mode) 10 Oscillating frequency, when using the built-in oscillating circuit (16 gradation fixed display mode) 11 Oscillating frequency, when using the built-in oscillating circuit (8 gradation fixed display mode) 12 Oscillating frequency, when using the built-in oscillating circuit (monochrome display mode) 13 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 6 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/9, 1/130 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" 14 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 5 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/12, 1/130 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" * This specification is subject to be changed without notice. 95 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
15 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 4 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/12, 1/130 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11"
16 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 3 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/12, 1/130 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11"
17 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 2 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/12, 1/130 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11"
18 VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 6 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display ALL ON pattern {Rf2, Rf1, Rf0 = ("0 0 0 ") }(on 4096 color display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE , VBA=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" , NLIN="0", (BF1,BF0)=(1,1),1/130 duty , 1/9 bias , BF="11" 19 VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 6 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display a checkered pattern ,{Rf2, Rf1, Rf0 = ("0 0 0 ") } (on 4096 color display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE , VBA=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" , NLIN="0" ,(BF1,BF0)=(1,1) ,1/130 duty , 1/9 bias, BF="11" 20 VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 5 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display ALL ON pattern ,{Rf2, Rf1, Rf0 = ("0 0 0 ") } (on 4096 color display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE , VBA=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" , NLIN="0" ,(BF1,BF0)=(1,1) ,1/130 duty , 1/9 bias, BF="11" 21 VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 5 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display a checkered pattern ,{Rf2, Rf1, Rf0 = ("0 0 0 ") } (on 4096 color display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE , VBA=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" , NLIN="0" ,(BF1,BF0)=(1,1) ,1/130 duty , 1/9 bias, BF="11"

22 VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 6 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display OFF ,{Rf2, Rf1, Rf0 = ("0 0 0 ") } (on mono color display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE , VBA=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" , NLIN="0" ,(BF1,BF0)=(1,1) ,1/130 duty , 1/9 bias, BF="11"
* This specification is subject to be changed without notice.
96
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
23 VREG pin. Measuring conditions: N times boosting(N=2~5), electronic control = "1 1 1 1 1 1 1" , Display a checkered pattern , DCON=AMPON="1" , NLIN="0" ,1/130 duty , VDD=VEE , VBA=VREF , C1=C2=1.0F, C3=0.1F , no load
Note: The capacitor C1 is use for booster related pin. CAP1+ , CAP1- , CAP2+ , CAP2- , CAP3+ , CAP3- , CAP4+ , CAP4- , CAP5+, CAP5- VOUT The capacitor C2 is use for bias related pin. V0 , V1 , V2 , V3 , V4 The capacitor C3 is use for VREG pin.
* This specification is subject to be changed without notice.
97
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
12. AC characteristic
(1) 80-family MCU write timing
tAS8
tAH8
CSB RS
tW RLW 8 W RB tDS8 tW RHW 8 tDH8
D0-D15
tCYCW R8
VSS=0V, VDD = 2.7~3.3V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 20 0 200 30 160 20 5 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS WRB (R/WB) D0~D15
VSS=0V, VDD = 2.4~2.7V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 30 0 300 40 250 30 10 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS WRB (R/WB) D0~D15
VSS=0V, VDD = 2.2~2.4V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 40 0 500 50 440 40 20 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS WRB (R/WB) D0~D15
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice. 98 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(2) 80-family MCU read timing
tAS8 CSB RS
tAH8
RDB
tRDLW 8 tRDHW 8 tRDH8
tRDD8 D0-D15
tCYCRD8
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 Condition Min. 0 0 380 200 170 10 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
CL = 80 pF
210
VSS=0V , VDD = 2.4~2.7V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 Condition Min. 0 0 540 290 230 10 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
CL = 80 pF
300
VSS=0V , VDD = 2.2~2.4V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 Condition Min. 0 0 840 440 380 10 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
CL = 80 pF
450
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice.
99
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(3) 68-family MCU write timing
tAS6 CSB RS
tAH6
R/W B (W RB)
E (RDB)
tEHW 6
tELW 6
tDS6
tDH6
D0-D15
tCYCW R6
VSS=0V , VDD = 2.7 ~3.3V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 20 0 200 160 30 20 5 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
VSS=0V , VDD = 2.4 ~2.7V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 30 0 300 250 40 30 10 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
VSS=0V , VDD = 2.2 ~2.4V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 40 0 500 440 50 40 20 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice. 100 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(4) 68-family MCU read timing
tAS6 CSB RS
tAH6
R/W B (W RB)
E (RDB)
tEHW 6
tELW 6
tRDD6
tRDH6
D0-D15
tCYCRD6
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in read Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 Condition Min. 0 0 380 200 170 10 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
CL=50pF
210
VSS=0V , VDD = 2.4~2.7V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in read Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 Condition Min. 0 0 540 290 230 10 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
CL=50pF
300
VSS=0V , VDD = 2.2~2.4V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in read Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 Condition Min. 0 0 1000 450 500 10 Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
CL=50pF
650
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice. 101 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(5) Serial interface timing diagram
tCSS CSB tCSH
RS tASS tSLW SCL tDSS tAHS
tSHW
tDHS
D0-D15
tCYCS
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85 Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 200 80 80 40 40 80 80 40 40 Typ. Max. Unit ns ns ns ns ns ns ns ns ns Pin used SCL RS SDA CSB
VSS=0V , VDD = 2.4~2.7V , Ta = -30~+85 Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 200 80 80 50 50 80 80 50 60 Typ. Max. Unit ns ns ns ns ns ns ns ns ns Pin used SCL RS SDA CSB
VSS=0V , VDD = 2.2~2.4V , Ta = -30~+85 Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 230 100 100 80 80 100 100 80 100 Typ. Max. Unit ns ns ns ns ns ns ns ns ns Pin used SCL RS SDA CSB
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice. 102 2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(6) Display control timing
tCLKH tCLKL CLK tDLP tDLP tLPLW LP tLPHW tDFLM
tDFLM FLM tDM
M
Input timing (Slave mode) VSS=0V , VDD = 2.4~3.3V , Ta = -30~+85 Item CLK pulse "H" width CLK pulse "L" width LP pulse "H" width LP pulse "L" width LP delay time FLM delay time M delay time Symbol tCLKH tCLKL tLPHW tLPLW tDLP tDFLM tDM Condition Min. 1.6 1.6 50 50 -1 -1 -1 Typ. Max. Unit s s s s s s s Pin used CLK LP FLM M
1 1 1
Input timing (Slave mode) VSS=0V , VDD = 2.2~2.4V , Ta = -30~+85 Item CLK pulse "H" width CLK pulse "L" width LP pulse "H" width LP pulse "L" width LP delay time FLM delay time M delay time Symbol tCLKH tCLKL tLPHW tLPLW tDLP tDFLM tDM Condition Min. 1.6 1.6 50 50 -1 -1 -1 Typ. Max. Unit s s s s s s s Pin used CLK LP FLM M
1 1 1
output timing (Master mode) VSS=0V , VDD = 2.4~3.3V , Ta = -30~+85 Item Symbol LP delay time tDLP FLM delay time tDFLM M delay time tDM Condition CL =15 pF Min. -500 -500 -500 Typ. Max. 500 500 500 Unit ns ns ns Pin used LP FLM M
output timing (Master mode) VSS=0V , VDD = 2.2~2.4V , Ta = -30~+85 Item Symbol LP delay time tDLP FLM delay time tDFLM M delay time tDM Condition CL =15 pF Min. -1000 -1000 -1000 Typ. Max. 1000 1000 1000 Unit s s s Pin used LP FLM M 2005/3/8 (V1.2)
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice. 103
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(7) Master clock input timing
tCKLW CK tCKHW
VSS=0V , VDD = 2.4~3.3V , Ta = -30~+85 Item CK pulse "H" width (1) CK pulse "L" width (1) CK pulse "H" width (2) CK pulse "L" width (2) CK pulse "H" width (3) CK pulse "L" width (3) Symbol tCKHW1 tCKLW1 tTCKHW2 tCKLW2 tCKHW3 tCKLW3 Condition Min. 1.2 1.2 5.4 5.4 3.8 3.8 Typ. Max. 1.4 1.4 6.5 6.5 4.5 4.5 Unit s s s s s s Pin used CK 1 CK 2 CK 3
VSS=0V , VDD = 2.2~2.4V , Ta = -30~+85 Item CK pulse "H" width (1) CK pulse "L" width (1) CK pulse "H" width (2) CK pulse "L" width (2) CK pulse "H" width (3) CK pulse "L" width (3) Symbol tCKHW1 tCKLW1 tCKHW2 tCKLW2 tCKHW3 tCKLW3 Condition Note1 Note1 Note2 Note2 Note3 Note3 Min. 1.2 1.2 5.4 5.4 3.8 3.8 Typ. Max. 1.4 1.4 6.5 6.5 4.5 4.5 Unit s s s s s s Pin used CK 1 CK 2 CK 3
1 Applied when the gradation display mode. MON="0" , PWM="0" 2 Applied when the simple gradation mode. MON="0" , PWM="1" 3 Applied when the monochrome mode. MON="1"
* This specification is subject to be changed without notice. 104
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(8) Reset timing
RESB
tRW tR
internal state
reset m ode
norm al dsiplay
VSS=0V, VDD = 2.4~3.3V, Ta = -30~+85 Item Reset time Reset pulse "L" width Symbol tR tRW Condition Min. 10 Typ. Max. 1 Unit s s Pin used RESB
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85 Item Reset time Reset pulse "L" width Symbol tR tRW Condition Min. 10 Typ. Max. 1.5 Unit s s Pin used RESB
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice. 105
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
13. Application circuit
(1) Connection to 80-family MCU
VCC A0 A1 to A7 80 family MPU Decoder /IORQ D0 to D15 /RD /WR /RES GND CSB RS
VDD
D0 to D15 RDB WRB RESB VSS
(2) Connection to 68-family MCU
VCC A0 A1 to A15 68 family MPU Decoder VMA D0 to D15 E R/W /RES GND CSB RS
VDD
D0 to D15 RDB(E) WRB(R/W) RESB VSS
* This specification is subject to be changed without notice. 106
EM65568
EM65568
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(3) Connection to the MCU with serial interface
VCC A0 RS
VDD
A1 to A7 MPU
Decoder
CSB EM65568 VSS
PORT1 PORT2 /RES GND
SDA SCL RESB
(4) Connection to Master / Slave about interface (parallel interface)
EM65568 (Master)
EM65568 (Slave)
D0-D15
D0-D15
RESB
RESB
WRB
WRB
RDB
RDB
CSB
M86
CSB
M86
M/S
M/S
R/S
R/S
P/S
P/S
VDD RESB CSB1 CSB2 RS WRB(R/W) RDB(E) D0-D7 M86
* This specification is subject to be changed without notice. 107
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(5) 4 wires type serial interface with two chip enable signals
EM65568 (Master)
SMODE SPOL SCL SDA RDB WRB P/S M86 M/S R/S CSB RESB VDD RESB CSB1 CSB2 RS SDA SCL
(6) 3 wires type serial interface with two chip enable signals
EM65568 (Slave)
SMODE SPOL SCL SDA RDB WRB P/S M86 M/S R/S CSB RESB
EM65568 (Master)
SMODE SPOL SCL SDA RDB WRB P/S M86 M/S R/S CSB RESB VDD RESB CSB1 CSB2 SDA SCL
* This specification is subject to be changed without notice. 108
EM65568 (Slave)
SMODE SPOL SCL SDA RDB WRB P/S M86 M/S R/S CSB RESB
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
(7) Connection to master / slave about power block
VDD VDD VEE VBA VREF VREG CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ CAP4CAP4+ CAP5CAP5+ VOUT V0 V1 V2 V3 V4 V1 V2 V3 V4 CLK LP FLM M EM65568 (Master) VDD VDD VEE VBA VREF VREG CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ CAP4EM65568 (Slave) CAP4+ CAP5CAP5+ VOUT V0 V1 V2 V3 V4 CLK LP FLM M
Caution of application about master / slave * The master chip control display timing (CLK,LP,FLM, and M). When making display OFF on the master chip, the master chip can not output the display timing. When making display OFF , beforehand set display OFF to the slave chip and set display OFF to the master chip. * When setting halt command, turn off the internal power supply, and output VSS level from LCD drive output pins , is set display OFF state. Because the master chip can not supply output voltage to the slave chip , beforehand set display OFF to the slave chip. *In above connection example, the master chip is only available the electronic volume control.
* This specification is subject to be changed without notice. 109
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
Tray Information
2X18
NH20-865X75-26
Tray Outline Dimensions Symbol L1 L2 L3 T Sx Sy S X Y Unit:mm Dimensions in mm 50.60 45.40 45.80 4.00 14.07 4.82 14.87 21.97 1.91 Symbol Z Px Py Nx Ny N P1 P2 Dimensions in mm 0.66 22.47 2.41 2 18 36 1.76 1.60
* This specification is subject to be changed without notice. 110
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
14. COF information
EM65568AF package
DESIGNED BY DRAWN BY CHECK BY APPROVED BY
UNIT: mm SCALE: GENERAL TOLERANCE .XX : .XXX :
* This specification is subject to be changed without notice. 111
DRAWING NO. REV SHEET
PART NO. CAD FILE
TITLE
2005/3/8 (V1.2)
EM65568 130 COM/ 128 SEG 4096 Color STN LCD Driver
EM65568BF package
EM65568BF
Elan
Elan Elan
DESIGNED BY DRAWN BY CHECK BY APPROVED BY
UNIT: mm SCALE: GENERAL TOLERANCE .XX : .XXX :
* This specification is subject to be changed without notice. 112
DRAWING NO. REV SHEET
PART NO. CAD FILE
TITLE

2005/3/8 (V1.2)

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